公开(公告)号：US20170133512A1

公开(公告)日：2017-05-11

申请号：US15104504

申请日：2015-07-17

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Zheng Liu ,  Chunping Long ,  Yu-Cheng Chan ,  Xiaoyong Lu ,  Xiaolong Li

IPC: H01L29/786 ,  H01L27/12 ,  H01L21/265 ,  H01L29/66 ,  H01L21/02

CPC classification number: H01L29/78633 ,  H01L21/02532 ,  H01L21/02592 ,  H01L21/02667 ,  H01L21/26513 ,  H01L27/1222 ,  H01L29/66757 ,  H01L29/78618 ,  H01L29/78675 ,  H01L29/78696

Abstract: The disclosure provides a polycrystalline silicon thin-film transistor and a method for manufacturing the same as well as a display device. The polycrystalline silicon thin-film transistor comprises: a substrate; an isolation layer formed on the substrate; and a polycrystalline silicon active layer formed on the substrate and the isolation layer, with two source-drain ion implantation regions being formed at both sides of the active layer, wherein the edges at both ends of the isolation layer are within the edges at both ends of the active layer. In the polycrystalline silicon thin-film transistor and the method for manufacturing the same provided by the disclosure, it is possible to increase the grain size of the active layer, improve the grain uniformity in a channel region thereof, effectively prevent deterioration of characteristics of the active layer caused by backlight irradiation, and improve the reliability of the device.

公开(公告)号：US09634043B2

公开(公告)日：2017-04-25

申请号：US14436563

申请日：2014-09-20

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Chunping Long ,  Jang Soon Im ,  Chien Hung Liu

IPC: H01L29/786 ,  H01L29/423 ,  H01L27/12 ,  H01L21/77 ,  G02F1/1343 ,  G02F1/1362 ,  G02F1/1368 ,  H01L27/32

CPC classification number: H01L27/1288 ,  G02F1/134363 ,  G02F1/136227 ,  G02F1/136286 ,  G02F1/1368 ,  G02F2001/136231 ,  G02F2001/13625 ,  H01L21/26513 ,  H01L21/266 ,  H01L21/77 ,  H01L27/12 ,  H01L27/124 ,  H01L27/1248 ,  H01L27/1255 ,  H01L27/1274 ,  H01L27/3248 ,  H01L27/3262 ,  H01L29/41733 ,  H01L29/42384 ,  H01L29/66757 ,  H01L29/78618 ,  H01L29/78675

Abstract: An array substrate, a manufacturing method thereof, a display device, a thin-film transistor (TFT) and a manufacturing method thereof are disclosed. The method for manufacturing the TFT comprises: forming a pattern of an active layer and a gate insulating layer provided with a metal film on a base substrate patterning the metal film by one patterning process, and forming patterns of a gate electrode a source electrode, a drain electrode a gate line and a data line; forming a passivation layer on the base substrate; patterning the passivation layer by one patterning process, and forming a source contact hole, a drain contact hole and a bridge structure contact hole; and forming a transparent conductive film on the base substrate, and removing partial transparent conductive film to form a source contact portion, a drain contact portion, a pixel electrode and a bridge structure.

公开(公告)号：US20160254298A1

公开(公告)日：2016-09-01

申请号：US14646925

申请日：2014-10-01

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Chunping Long ,  Yinan Liang ,  Lujiang Huangfu

IPC: H01L27/12 ,  H01L21/28 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L27/1288 ,  H01L21/28008 ,  H01L21/28158 ,  H01L21/28506 ,  H01L27/12 ,  H01L27/1262 ,  H01L27/127 ,  H01L27/1274 ,  H01L27/3244 ,  H01L29/66765 ,  H01L29/78678 ,  H01L29/78696 ,  H01L2251/5315

Abstract: An array substrate, a manufacturing method thereof and a display device are disclosed. Patterns comprising a gate, a gate insulating layer and a polysilicon active layer are formed on a base substrate by single patterning process. A passivation layer is formed on the substrate surface formed with the patterns, and patterns of a first via and a second via are formed on a surface of the passivation layer by single patterning process. Patterns of a source, a drain and a pixel electrode are formed on the substrate surface formed with the patterns by single patterning process. The source is electrically connected with the polysilicon active layer through the first via, and the drain is electrically connected with the polysilicon active layer through the second via. A pattern of pixel defining layer is formed on the substrate surface formed with the patterns by single patterning process.

Abstract translation: 公开了阵列基板，其制造方法和显示装置。 通过单一图案化工艺在基底基板上形成包括栅极，栅极绝缘层和多晶硅有源层的图案。 在形成有图案的基板表面上形成钝化层，并且通过单一图案化工艺在钝化层的表面上形成第一通孔和第二通孔的图案。 通过单一图案化工艺，在形成有图案的衬底表面上形成源极，漏极和像素电极的图案。 源极通过第一通孔与多晶硅有源层电连接，漏极通过第二通孔与多晶硅有源层电连接。 通过单一图案化工艺在形成有图案的衬底表面上形成像素限定层的图案。

公开(公告)号：US08940625B2

公开(公告)日：2015-01-27

申请号：US13980478

申请日：2012-12-10

Applicant: Boe Technology Group Co., Ltd.

Inventor： Xueyan Tian ,  Chunping Long ,  Jiangfeng Yao

IPC: H01L21/20 ,  H01L21/02 ,  C23C16/24 ,  H01L21/268 ,  H01L21/3205 ,  C23C16/02 ,  C23C16/56

CPC classification number: H01L21/02502 ,  C23C16/0272 ,  C23C16/24 ,  C23C16/56 ,  H01L21/0245 ,  H01L21/02488 ,  H01L21/02505 ,  H01L21/02513 ,  H01L21/02516 ,  H01L21/02532 ,  H01L21/02595 ,  H01L21/02675 ,  H01L21/02686 ,  H01L21/268 ,  H01L21/32055

Abstract: An embodiment of the present invention relates to a low temperature polysilicon thin film and a manufacturing method thereof. The manufacturing method comprises: forming a buffer layer on a substrate (S11); forming a seed layer comprising a plurality of uniformly distributed crystal nuclei on the buffer layer by using a patterning process (S12); forming an amorphous silicon layer on the seed layer (S13); and performing an excimer laser annealing process on the amorphous silicon layer (S14).

Abstract translation: 本发明的实施例涉及一种低温多晶硅薄膜及其制造方法。 制造方法包括：在基板上形成缓冲层（S11）; 通过图案化工艺在缓冲层上形成包含多个均匀分布的晶核的晶种层（S12）; 在籽晶层上形成非晶硅层（S13）; 对非晶硅层进行准分子激光退火处理（S14）。

公开(公告)号：US12191421B2

公开(公告)日：2025-01-07

申请号：US17761253

申请日：2021-03-19

Applicant: BEIJING BOE TECHNOLOGY DEVELOPMENT CO., LTD. ,  BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Chunping Long ,  Qi Qi ,  Xinxin Zhao ,  Wanzhi Chen

IPC: H01L33/38 ,  H01L25/075 ,  H01L25/16 ,  H01L33/62

Abstract: A light emitting substrate and a display device are provided, the light emitting substrate includes: a base substrate: an electrode planarization layer, on the base substrate: an electrode layer, at a side of the electrode planarization layer away from the base substrate, the electrode layer includes a first electrode and a second electrode, the first electrode includes at least one first electrode strip, the second electrode includes at least one second electrode strip, the first electrode strip and the second electrode strip are spaced and alternately arranged in a first direction, each of the at least one first electrode strip and each of the at least one second electrode strip extend along a second direction, the electrode planarization layer includes a first groove between a first electrode strip and a second electrode strip which are adjacent to each other, the first groove is configured to accommodate a light emitting diode.

公开(公告)号：US11940700B2

公开(公告)日：2024-03-26

申请号：US16982347

申请日：2020-04-14

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Chunping Long ,  Hui Li

IPC: G02F1/1368 ,  G02F1/1362 ,  H01L27/12

CPC classification number: G02F1/1368 ,  G02F1/136286 ,  H01L27/124

Abstract: The present disclosure relates to an array substrate, a display panel, and a display device. The array substrate comprises a display area and a non-display area surrounding the display area; wherein: the display area includes gate lines and data lines, and a plurality of pixel units defined by the intersections of gate lines and data lines, each of the pixel units including a thin film transistor and a pixel electrode electrically connected to a drain electrode of the thin film transistor; the non-display area includes a plurality of dummy pixel units arranged around the display area, each of the dummy pixel units including a dummy thin film transistor and a dummy pixel electrode floating relative to a drain electrode of the dummy thin film transistor; the non-display area further includes a dummy common electrode structure electrically connected to at least some of the dummy pixel units.

公开(公告)号：US11495594B2

公开(公告)日：2022-11-08

申请号：US16340186

申请日：2018-08-02

Applicant: BOE Technology Group Co., Ltd.

Inventor： Chunping Long ,  Yong Qiao ,  Xinyin Wu

IPC: H01L27/02 ,  H01L27/12 ,  H02H9/04

Abstract: An electrostatic protection circuit and a manufacturing method thereof, an array substrate, and a display device are provided. The electrostatic protection circuit includes: at least one first transistor and at least one second transistor. A gate electrode and a first electrode of the first transistor are connected to a first signal line, and a second electrode of the first transistor is connected to a second signal line. A gate electrode and a first electrode of the second transistor are connected to the second signal line, and a second electrode of the second transistor is connected to the first signal line.

公开(公告)号：US11387259B2

公开(公告)日：2022-07-12

申请号：US17280795

申请日：2020-07-21

Applicant: BEIJING BOE TECHNOLOGY DEVELOPMENT CO., LTD. ,  BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Pan Li ,  Jianbo Xian ,  Chunping Long

IPC: H01L27/12 ,  H01L51/52

Abstract: The present disclosure provides an array substrate, a manufacturing method thereof, and a display device. The array substrate includes a base substrate, and a first functional layer and a second functional layer laminated one on another on the base substrate. The first functional layer forms a level-different region on the base substrate, and the second functional layer covers the level-different region. A portion of the first functional layer at the level-different region is provided with a target gradient angle, the target gradient angle is a maximum gradient angle when the second functional layer has a predetermined thickness, and the predetermined thickness is a thickness when a functional requirement of the second functional layer has been met and the second functional layer is not broken at the level-different region.

公开(公告)号：US11328644B2

公开(公告)日：2022-05-10

申请号：US17255920

申请日：2020-05-13

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Chunping Long ,  Hui Li

IPC: G09G3/20 ,  G06F3/041

Abstract: Provided are an array substrate and a display panel. The array substrate includes: gate lines and data lines on a substrate, the gate lines extending in a first direction, the data lines extending in a second direction, and the gate lines and the data lines crossing over each other to define pixel regions arranged in a matrix; pixel electrodes respectively in the plurality of pixel regions and on a side of the gate lines away from the substrate; common electrode lines at least partially surrounding the plurality of pixel regions; and a shielding electrode on a side of the gate lines away from the substrate and electrically connected to the common electrode lines, an orthographic projection of the shielding electrode on the substrate covering an orthographic projection of a portion, between the pixel electrodes adjacent in the second direction, of at least one of the gate lines on the substrate.

公开(公告)号：US11315920B2

公开(公告)日：2022-04-26

申请号：US16956483

申请日：2019-11-21

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Chunping Long

IPC: H01L27/02 ,  H01L27/12 ,  H01L21/66

Abstract: An array substrate includes a base substrate, at least one first signal line and at least one second signal line disposed at a first side of the base substrate, and at least one electrostatic discharge (ESD) protection device disposed at the first side of the base substrate. Each ESD protection device includes a first electrode coupled to one first signal line, a second electrode coupled to one second signal line, and an insulating medium disposed between the first electrode and the second electrode. An orthographic projection of the first electrode on the base substrate at least partially overlaps with an orthographic projection of the second electrode on the base substrate, and the ESD protection device is configured to discharge electrostatic charges on one of the first signal line and the second signal line that are coupled to the ESD protection device to the other one.