公开(公告)号：US11145808B2

公开(公告)日：2021-10-12

申请号：US16681351

申请日：2019-11-12

Applicant: Applied Materials, Inc.

Inventor： Jong Mun Kim ,  Minrui Yu ,  Chando Park ,  Mang-Mang Ling ,  Jaesoo Ahn ,  Chentsau Chris Ying ,  Srinivas D. Nemani ,  Mahendra Pakala ,  Ellie Y. Yieh

IPC: H01L43/12 ,  H01L43/10 ,  H01L43/02 ,  H01L27/22

Abstract: Embodiments of the disclosure provide methods and apparatus for fabricating magnetic tunnel junction (MTJ) structures on a substrate for MRAM applications. In one embodiment, a method for forming a magnetic tunnel junction (MTJ) device structure includes performing a patterning process by an ion beam etching process in a processing chamber to pattern a film stack disposed on a substrate, wherein the film stack comprises a reference layer, a tunneling barrier layer and a free layer disposed on the tunneling barrier, and determining an end point for the patterning process.

公开(公告)号：US20210234091A1

公开(公告)日：2021-07-29

申请号：US16752013

申请日：2020-01-24

Applicant: APPLIED Materials, Inc.

Inventor： Jong Mun Kim ,  Mang-Mang Ling ,  Soham Asrani ,  Lin Xue ,  Chentsau Chris Ying ,  Srinivas D. Nemani ,  Ellie Y. Yieh

IPC: H01L43/12 ,  H01L43/10

Abstract: A method of etching a layer stack. The method may include providing a substrate in a process chamber, the substrate comprising an array of patterned features, arranged within a layer stack, the layer stack including at least one metal layer, and directing an ion beam to the substrate from an ion source, wherein the ion beam causes a physical sputtering of the at least one metal layer. The method may include directing a neutral reactive gas directly to the substrate, separately from the ion source, wherein the neutral reactive gas reacts with metallic species generated by the physical sputtering of the at least one metal layer.

公开(公告)号：US20200350178A1

公开(公告)日：2020-11-05

申请号：US16901210

申请日：2020-06-15

Applicant: Applied Materials, Inc.

Inventor： He Ren ,  Jong Mun Kim ,  Maximillian Clemons ,  Minrui Yu ,  Mehul Naik ,  Chentsau Ying

IPC: H01L21/3213

Abstract: Exemplary methods of etching semiconductor substrates may include flowing a halogen-containing precursor into a processing region of a semiconductor processing chamber. The processing region may house a substrate having a conductive material and an overlying mask material. The conductive material may be characterized by a first surface in contact with the mask material, and the mask material may define an edge region of the conductive material. The methods may include contacting the edge region of the conductive material with the halogen-containing precursor and the oxygen-containing precursor. The methods may include etching in a first etching operation the edge region of the conductive material to a partial depth through the conductive material to produce a footing of conductive material protruding along the edge region of the conductive material. The methods may also include removing the footing of conductive material in a second etching operation.

公开(公告)号：US09748366B2

公开(公告)日：2017-08-29

申请号：US14491828

申请日：2014-09-19

Applicant: Applied Materials, Inc.

Inventor： Jong Mun Kim ,  Kenny L. Doan ,  Li Ling ,  Jairaj Payyapilly ,  Srinivas D. Nemani ,  Daisuke Shimizu ,  Yuju Huang

IPC: H01L21/31 ,  H01L29/66 ,  H01L21/311

CPC classification number: H01L29/66833 ,  H01L21/31116

Abstract: An article having alternating oxide layers and nitride layers is etched by an etch process. The etch process includes providing a first gas comprising C4F6H2 in a chamber of an etch reactor, ionizing the C4F6H2 containing gas to produce a plasma comprising a plurality of ions, and etching the article using the plurality of ions.

公开(公告)号：US09269587B2

公开(公告)日：2016-02-23

申请号：US14020773

申请日：2013-09-06

Applicant: Applied Materials, Inc.

Inventor： Daisuke Shimizu ,  Jong Mun Kim ,  Katsumasa Kawasaki ,  Sergio Fukuda Shoji

IPC: H01L21/3065 ,  H01L21/311 ,  H01J37/32

CPC classification number: H01L21/3065 ,  H01J37/32091 ,  H01J2237/334 ,  H01L21/31116

Abstract: Embodiments of the present invention provide methods for etching a material layer using synchronized RF pulses. In one embodiment, a method includes providing a gas mixture into a processing chamber, applying a first RF source power at a first time point to the processing chamber to form a plasma in the gas mixture, applying a first RF bias power at a second time point to the processing chamber to perform an etching process on the substrate, turning off the first RF bias power at a third time point while continuously maintaining the first RF source power on from the first time point through the second and the third time points, and turning off the first RF source power at a fourth time point while continuously providing the gas mixture to the processing chamber from the first time point through the second, third and fourth time points.

Abstract translation: 本发明的实施例提供了使用同步RF脉冲来蚀刻材料层的方法。 在一个实施例中，一种方法包括将气体混合物提供到处理室中，在第一时间点将第一RF源功率施加到处理室以在气体混合物中形成等离子体，在第二时间施加第一RF偏置功率 指向处理室，以对基板执行蚀刻处理，在第三时间点关闭第一RF偏置功率，同时从第一时间点到第二时间点和第三时间点持续保持第一RF源功率接通，以及 在第四时间点关闭第一RF源功率，同时从第一时间点到第二，第三和第四时间点连续地将气体混合物提供到处理室。

公开(公告)号：US20240321641A1

公开(公告)日：2024-09-26

申请号：US18606739

申请日：2024-03-15

Applicant: Applied Materials, Inc.

Inventor： Hao Jiang ,  Jong Mun Kim ,  Jonathan Qian ,  He Ren ,  Mehul Naik

IPC: H01L21/822 ,  H01L21/311

CPC classification number: H01L21/8221 ,  H01L21/31116

Abstract: A method includes forming a planarization layer to a position below an upper transistor device region of a base structure of an electronic device and above a lower transistor device region of the base structure. The base structure includes a plurality of features. The method further includes forming spacer material along the base structure and the planarization layer, modifying the spacer material formed along bottom trenches of the base structure to obtain modified spacer material, and forming a spacer layer by using a wet etch process to remove the modified spacer material. Modifying the spacer material formed along the bottom trenches of the base structure to obtain the modified spacer material includes performing a dry etch process targeting the spacer material formed along the bottom trenches of the base structure.

公开(公告)号：US11384428B2

公开(公告)日：2022-07-12

申请号：US16904396

申请日：2020-06-17

Applicant: Applied Materials, Inc.

Inventor： Mang-Mang Ling ,  Thomas Kwon ,  Jong Mun Kim ,  Chentsau Chris Ying

IPC: C23C16/04 ,  C23C16/26 ,  H01L27/11582 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11524 ,  C23C14/35 ,  C23C14/04 ,  C23C16/511 ,  C23C14/58 ,  C23C14/06

Abstract: Embodiments of the present disclosure generally relate to a method for forming an opening using a mask. In one embodiment, a method includes forming a mask on a feature layer. The method includes forming a first opening in the mask to expose a portion of the feature layer. The method further includes forming a carbon layer on the mask and the exposed portion of the feature layer. The method also includes removing portions of the carbon layer and a portion of the exposed portion of the feature layer in order to form a second opening in the feature layer.

公开(公告)号：US11289342B2

公开(公告)日：2022-03-29

申请号：US16901210

申请日：2020-06-15

Applicant: Applied Materials, Inc.

Inventor： He Ren ,  Jong Mun Kim ,  Maximillian Clemons ,  Minrui Yu ,  Mehul Naik ,  Chentsau Ying

IPC: H01L21/321 ,  H01L21/3213

Abstract: Exemplary methods of etching semiconductor substrates may include flowing a halogen-containing precursor into a processing region of a semiconductor processing chamber. The processing region may house a substrate having a conductive material and an overlying mask material. The conductive material may be characterized by a first surface in contact with the mask material, and the mask material may define an edge region of the conductive material. The methods may include contacting the edge region of the conductive material with the halogen-containing precursor and the oxygen-containing precursor. The methods may include etching in a first etching operation the edge region of the conductive material to a partial depth through the conductive material to produce a footing of conductive material protruding along the edge region of the conductive material. The methods may also include removing the footing of conductive material in a second etching operation.

公开(公告)号：US10964527B2

公开(公告)日：2021-03-30

申请号：US16401883

申请日：2019-05-02

Applicant: Applied Materials, Inc.

Inventor： Jong Mun Kim ,  Biao Liu ,  Cheng Pan ,  Erica Chen ,  Chentsau Ying ,  Srinivas Nemani ,  Ellie Yieh

IPC: H01L21/02 ,  H01L21/3105 ,  H01L21/311

Abstract: Methods for removing residuals after a selective deposition process are provided. In one embodiment, the method includes performing a selective deposition process to form a metal containing dielectric material at a first location of a substrate and performing a residual removal process to remove residuals from a second location of the substrate.

公开(公告)号：US10957548B2

公开(公告)日：2021-03-23

申请号：US16683828

申请日：2019-11-14

Applicant: APPLIED MATERIALS, INC.

Inventor： Mang-Mang Ling ,  Jong Mun Kim ,  Chentsau Ying

IPC: H01L21/308 ,  H01L21/3065 ,  C09K13/10 ,  C01B19/00 ,  H01L21/67

Abstract: Methods for dry plasma etching thin layers of material including Cu(In, Ga)Se, e.g., CIGS material on semiconductor substrates are provided. A method of etching a CIGS material layer such as copper indium gallium selenide film, includes: flowing an etching gas including a mixture of gases into a process chamber having a substrate disposed therein, the substrate including a copper indium gallium selenide layer having a patterned film stack disposed thereon, the patterned film stack covering a first portion of the copper indium gallium selenide layer and exposing a second portion of the copper indium gallium selenide layer; and contacting the copper indium gallium selenide layer with the etching gas to remove the second portion and form one or more copper indium gallium selenide edges of the first portion.