公开(公告)号：US20240321641A1

公开(公告)日：2024-09-26

申请号：US18606739

申请日：2024-03-15

Applicant: Applied Materials, Inc.

Inventor： Hao Jiang ,  Jong Mun Kim ,  Jonathan Qian ,  He Ren ,  Mehul Naik

IPC: H01L21/822 ,  H01L21/311

CPC classification number: H01L21/8221 ,  H01L21/31116

Abstract: A method includes forming a planarization layer to a position below an upper transistor device region of a base structure of an electronic device and above a lower transistor device region of the base structure. The base structure includes a plurality of features. The method further includes forming spacer material along the base structure and the planarization layer, modifying the spacer material formed along bottom trenches of the base structure to obtain modified spacer material, and forming a spacer layer by using a wet etch process to remove the modified spacer material. Modifying the spacer material formed along the bottom trenches of the base structure to obtain the modified spacer material includes performing a dry etch process targeting the spacer material formed along the bottom trenches of the base structure.