公开(公告)号：US20230035288A1

公开(公告)日：2023-02-02

申请号：US17858371

申请日：2022-07-06

Applicant: Applied Materials, Inc.

Inventor： Suketu PARIKH ,  Andrew YEOH ,  Tom S. CHOI ,  Joung Joo LEE ,  Nitin K. INGLE

IPC: H01L21/311 ,  H01L21/768

Abstract: Methods open etch stop layers in an integrated environment along with metallization processes. In some embodiments, a method for opening an etch stop layer (ESL) prior to metallization may include etching the ESL with an anisotropic process using direct plasma to form helium ions that are configured to roughen the ESL for a first duration of approximately 10 seconds to approximately 30 seconds, forming aluminum fluoride on the ESL using remote plasma and nitrogen trifluoride gas for a second duration of approximately 10 seconds to approximately 30 seconds, and exposing the ESL to a gas mixture of boron trichloride, trimethylaluminum, and/or dimethylaluminum chloride at a temperature of approximately 100 degrees Celsius to approximately 350 degrees Celsius to remove aluminum fluoride from the ESL and a portion of a material of the ESL for a third duration of approximately 30 seconds to approximately 60 seconds.

公开(公告)号：US20230031381A1

公开(公告)日：2023-02-02

申请号：US17858390

申请日：2022-07-06

Applicant: Applied Materials, Inc.

Inventor： Suketu PARIKH ,  Andrew YEOH ,  Tom S. CHOI ,  Joung Joo LEE ,  Nitin K. INGLE

IPC: H01L21/02 ,  H01L21/311 ,  H01L21/768

Abstract: In some embodiments, an integrated tool for opening an etch stop layer and performing metallization comprises a first chamber with a remote plasma source, a direct plasma source, and a thermal source configured to open the etch stop layer on a substrate, a second chamber of the integrated tool with dry etch processing configured to pre-clean surfaces exposed by opening the etch stop layer, a third chamber of the integrated tool configured to deposit a barrier layer on the substrate, a fourth chamber of the integrated tool configured to deposit a liner layer on the substrate, and at least one fifth chamber of the integrated tool configured to deposit metallization material on the substrate. The integrated tool may also include a vacuum transfer chamber.

公开(公告)号：US20220130722A1

公开(公告)日：2022-04-28

申请号：US17505521

申请日：2021-10-19

Applicant: Applied Materials, Inc.

Inventor： Suketu Arun PARIKH ,  Martin Jay SEAMONS ,  Jingmei LIANG ,  Shuchi Sunil OJHA ,  Tom CHOI ,  Nitin K. INGLE ,  Sanjay NATARAJAN

IPC: H01L21/768

Abstract: A substrate processing method includes creating a mask on a top surface of a workpiece. A first portion of a gap fill material is overlaid by the mask and a second portion of the gap fill material is exposed through an opening in the mask. The method further includes exposing the workpiece to a plasma. The method further includes performing a first etching of the first portion of the gap fill material to create a first cavity while the second portion of the gap fill material remains in place, depositing a first metal-containing substance in the first cavity, performing a second etching of the second portion of the gap fill material to create a second cavity while the first metal-containing substance remains in place, and depositing a second metal-containing substance in the second cavity.

公开(公告)号：US20180254187A1

公开(公告)日：2018-09-06

申请号：US15966787

申请日：2018-04-30

Applicant: Applied Materials, Inc.

Inventor： Vinod Robert PURAYATH ,  Nitin K. INGLE

IPC: H01L21/28 ,  H01L29/06 ,  H01L27/1157 ,  H01L27/11582

CPC classification number: H01L29/40117 ,  H01L27/1157 ,  H01L27/11582 ,  H01L29/0649

Abstract: In a 3D NAND device, the charge trap region of a memory cell is formed as a separate charge-trap “island.” As a result, the charge-trap region of one memory cell is electrically isolated from charge-trap regions in adjacent memory cells. The charge trap region of one memory cell is separated from the charge trap regions of adjacent memory cells by a dielectric structure, such as a silicon oxide film. Alternatively, the charge trap region of a memory cell is separated from the charge trap regions of adjacent memory cells by an air, gas, or vacuum gap.

公开(公告)号：US20180182777A1

公开(公告)日：2018-06-28

申请号：US15855465

申请日：2017-12-27

Applicant: Applied Materials, Inc.

Inventor： Zhenjiang CUI ,  Hanshen ZHANG ,  Anchuan WANG ,  Zhijun CHEN ,  Nitin K. INGLE

IPC: H01L27/11582 ,  H01L21/311 ,  H01L21/3213 ,  H01L23/31 ,  H01L23/29 ,  H01L27/11556 ,  H01L21/67

Abstract: Embodiments of the present disclosure provide methods for forming features in a film stack. The film stack may be utilized to form stair-like structures with accurate profiles control in manufacturing three dimensional (3D) stacking of semiconductor chips. In one example, a method includes exposing a substrate having a multi-material layer formed thereon to radicals of a remote plasma to form one or more features through the multi-material layer, the one or more features exposing a portion of a top surface of the substrate, and the multi-material layer comprising alternating layers of a first layer and a second layer, wherein the remote plasma is formed from an etching gas mixture comprising a fluorine-containing chemistry, and wherein the process chamber is maintained at a pressure of about 2 Torr to about 20 Torr and a temperature of about −100° C. to about 100° C.

公开(公告)号：US20150126045A1

公开(公告)日：2015-05-07

申请号：US14520721

申请日：2014-10-22

Applicant: Applied Materials, Inc.

Inventor： Amit CHATTERJEE ,  Abhijit Basu MALLICK ,  Nitin K. INGLE

IPC: H01L21/02

CPC classification number: H01L21/0217 ,  C23C16/345 ,  C23C16/4411 ,  C23C16/452 ,  C23C16/45582 ,  H01L21/02211 ,  H01L21/02219 ,  H01L21/02222 ,  H01L21/02274

Abstract: Embodiments of the present invention generally provide methods for forming a silicon nitride layer on a substrate. In one embodiment, a method of forming a silicon nitride layer using remote plasma chemical vapor deposition (CVD) at a temperature that is less than 300 degrees Celsius is disclosed. The precursors for the remote plasma CVD process include tris(dimethylamino)silane (TRIS), dichlorosilane (DCS), trisilylamine (TSA), bis-t-butylaminosilane (BTBAS), hexachlorodisilane (HCDS) or hexamethylcyclotrisilazane (HMCTZ).

Abstract translation: 本发明的实施方案通常提供在衬底上形成氮化硅层的方法。 在一个实施例中，公开了在小于300摄氏度的温度下使用远程等离子体化学气相沉积（CVD）形成氮化硅层的方法。 用于远程等离子体CVD工艺的前体包括三（二甲基氨基）硅烷（TRIS），二氯硅烷（DCS），三甲基胺（TSA），双 - 叔丁基氨基硅烷（BTBAS），六氯二硅烷（HCDS）或六甲基环三硅氮烷（HMCTZ）。

公开(公告)号：US20140271097A1

公开(公告)日：2014-09-18

申请号：US14188344

申请日：2014-02-24

Applicant: APPLIED MATERIALS, INC.

Inventor： Anchuan WANG ,  Xinglong CHEN ,  Zihui LI ,  Hiroshi HAMANA ,  Zhijun CHEN ,  Ching-Mei HSU ,  Jiayin HUANG ,  Nitin K. INGLE ,  Dmitry LUBOMIRSKY ,  Shankar VENKATARAMAN ,  Randhir THAKUR

IPC: H01L21/677

CPC classification number: H01L21/324 ,  C23C16/4405 ,  H01J37/32357 ,  H01J37/32862 ,  H01L21/02041 ,  H01L21/02057 ,  H01L21/0206 ,  H01L21/263 ,  H01L21/2686 ,  H01L21/30604 ,  H01L21/3065 ,  H01L21/3105 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/32136 ,  H01L21/32137 ,  H01L21/67069 ,  H01L21/67075 ,  H01L21/6708 ,  H01L21/67109 ,  H01L21/67115 ,  H01L21/67184 ,  H01L21/6719 ,  H01L21/67196 ,  H01L21/67201 ,  H01L21/67207 ,  H01L21/67248 ,  H01L21/67253 ,  H01L21/67288 ,  H01L21/67703 ,  H01L21/67739 ,  H01L21/67742 ,  H01L21/6831

Abstract: Systems, chambers, and processes are provided for controlling process defects caused by moisture contamination. The systems may provide configurations for chambers to perform multiple operations in a vacuum or controlled environment. The chambers may include configurations to provide additional processing capabilities in combination chamber designs. The methods may provide for the limiting, prevention, and correction of aging defects that may be caused as a result of etching processes performed by system tools.

Abstract translation: 提供系统，室和过程以控制由水分污染引起的过程缺陷。 这些系统可以提供腔室的配置，以在真空或受控环境中执行多个操作。 腔室可以包括在组合腔室设计中提供附加处理能力的构造。 这些方法可以提供由系统工具执行的蚀刻工艺可能引起的老化缺陷的限制，预防和校正。