公开(公告)号：US20240387458A1

公开(公告)日：2024-11-21

申请号：US18199183

申请日：2023-05-18

Applicant: Applied Materials, Inc.

Inventor： Suketu PARIKH ,  Andrew YEOH ,  Arvind SUNDARRAJAN ,  Nirmalya MAITY ,  Balasubramanian PRANATHARTHIHARAN ,  Martinus Maria BERKENS

IPC: H01L25/065 ,  H01L21/768 ,  H01L21/78 ,  H01L23/00 ,  H01L23/367 ,  H01L23/522 ,  H01L25/00

Abstract: In some embodiments, a method for forming a multiple die stack comprises forming a first circuit wafer with multiple first circuit dies and a first circuit support layer on a bottom of the first circuit wafer where each first circuit die has a power and circuit layer underlying a power and signal layer, forming an interposer wafer with multiple interposer dies and an interposer support layer on a top of the interposer wafer where each interposer die has a power and signal layer underlying a power via and signal via layer, and hybrid bonding a top surface of the first circuit wafer to a bottom surface of the interposer wafer to form a first bonded wafer with electrical power and signal connections between the multiple first circuit dies and the multiple interposer dies where the interposer wafer provides structural support of the first bonded wafer during subsequent processing.

公开(公告)号：US20250063797A1

公开(公告)日：2025-02-20

申请号：US18762053

申请日：2024-07-02

Applicant: Applied Materials, Inc.

Inventor： Kyoung Ha KIM ,  Veeraraghavan S. BASKER ,  Byeong Chan LEE ,  Andrew YEOH

IPC: H01L29/417 ,  H01L21/283 ,  H01L21/3065 ,  H01L29/06 ,  H01L29/423 ,  H01L29/45 ,  H01L29/775 ,  H01L29/786

Abstract: A method of forming a portion of a gate-all-around field-effect transistor includes performing a selective deposition process to form selective cap layers at bottoms of contact trenches formed within portions of a substrate isolated by shallow trench isolations (STIs), wherein the contact trenches each interface with an S/D epitaxial (epi) layer with an extension region, performing a substrate angled etch process to etch sidewalls of the contact trenches, enlarging top critical dimension (CD) of the contact trenches, performing a substrate selective removal plasma (SRP) etch process to isotropically etch the substrate within the contact trenches, performing a recess fill process to fill the contact trenches with dielectric layers, performing an inter-layer dielectric (ILD) recess process to partially remove the substrate between the dielectric layers within the contact trenches and form an ILD recess, and performing a substrate isotropic etch process to partially remove the substrate within the ILD recess.

公开(公告)号：US20230035288A1

公开(公告)日：2023-02-02

申请号：US17858371

申请日：2022-07-06

Applicant: Applied Materials, Inc.

Inventor： Suketu PARIKH ,  Andrew YEOH ,  Tom S. CHOI ,  Joung Joo LEE ,  Nitin K. INGLE

IPC: H01L21/311 ,  H01L21/768

Abstract: Methods open etch stop layers in an integrated environment along with metallization processes. In some embodiments, a method for opening an etch stop layer (ESL) prior to metallization may include etching the ESL with an anisotropic process using direct plasma to form helium ions that are configured to roughen the ESL for a first duration of approximately 10 seconds to approximately 30 seconds, forming aluminum fluoride on the ESL using remote plasma and nitrogen trifluoride gas for a second duration of approximately 10 seconds to approximately 30 seconds, and exposing the ESL to a gas mixture of boron trichloride, trimethylaluminum, and/or dimethylaluminum chloride at a temperature of approximately 100 degrees Celsius to approximately 350 degrees Celsius to remove aluminum fluoride from the ESL and a portion of a material of the ESL for a third duration of approximately 30 seconds to approximately 60 seconds.

公开(公告)号：US20230031381A1

公开(公告)日：2023-02-02

申请号：US17858390

申请日：2022-07-06

Applicant: Applied Materials, Inc.

Inventor： Suketu PARIKH ,  Andrew YEOH ,  Tom S. CHOI ,  Joung Joo LEE ,  Nitin K. INGLE

IPC: H01L21/02 ,  H01L21/311 ,  H01L21/768

Abstract: In some embodiments, an integrated tool for opening an etch stop layer and performing metallization comprises a first chamber with a remote plasma source, a direct plasma source, and a thermal source configured to open the etch stop layer on a substrate, a second chamber of the integrated tool with dry etch processing configured to pre-clean surfaces exposed by opening the etch stop layer, a third chamber of the integrated tool configured to deposit a barrier layer on the substrate, a fourth chamber of the integrated tool configured to deposit a liner layer on the substrate, and at least one fifth chamber of the integrated tool configured to deposit metallization material on the substrate. The integrated tool may also include a vacuum transfer chamber.