公开(公告)号：US20200051994A1

公开(公告)日：2020-02-13

申请号：US16150652

申请日：2018-10-03

Applicant: Applied Materials, Inc.

Inventor： Vinod Robert PURAYATH ,  Priyadarshi PANDA ,  Abhijit MALLICK ,  Srinivas GANDIKOTA

IPC: H01L27/11582 ,  H01L27/1157 ,  H01L27/11524 ,  H01L27/11556

Abstract: A method of forming a memory device including a plurality of nonvolatile memory cells is provided. The method includes forming a hole in a stack of alternating insulator layers and memory cell layers. The stack extends from a bottom to a top, and the stack includes a plurality of insulator layers and plurality of memory cell layers. The method further includes depositing a first portion of a silicon channel layer. The first portion of the silicon channel layer extends from the bottom of the stack to the top of the stack. The method further includes adding a dopant layer over the first portion of the silicon channel layer. The dopant layer includes a first dopant. The method further includes depositing a second portion of the silicon channel layer. The second portion of the silicon channel layer extends from the bottom of the stack to the top of the stack.

公开(公告)号：US20180254187A1

公开(公告)日：2018-09-06

申请号：US15966787

申请日：2018-04-30

Applicant: Applied Materials, Inc.

Inventor： Vinod Robert PURAYATH ,  Nitin K. INGLE

IPC: H01L21/28 ,  H01L29/06 ,  H01L27/1157 ,  H01L27/11582

CPC classification number: H01L29/40117 ,  H01L27/1157 ,  H01L27/11582 ,  H01L29/0649

Abstract: In a 3D NAND device, the charge trap region of a memory cell is formed as a separate charge-trap “island.” As a result, the charge-trap region of one memory cell is electrically isolated from charge-trap regions in adjacent memory cells. The charge trap region of one memory cell is separated from the charge trap regions of adjacent memory cells by a dielectric structure, such as a silicon oxide film. Alternatively, the charge trap region of a memory cell is separated from the charge trap regions of adjacent memory cells by an air, gas, or vacuum gap.