公开(公告)号：US11289342B2

公开(公告)日：2022-03-29

申请号：US16901210

申请日：2020-06-15

Applicant: Applied Materials, Inc.

Inventor： He Ren ,  Jong Mun Kim ,  Maximillian Clemons ,  Minrui Yu ,  Mehul Naik ,  Chentsau Ying

IPC: H01L21/321 ,  H01L21/3213

Abstract: Exemplary methods of etching semiconductor substrates may include flowing a halogen-containing precursor into a processing region of a semiconductor processing chamber. The processing region may house a substrate having a conductive material and an overlying mask material. The conductive material may be characterized by a first surface in contact with the mask material, and the mask material may define an edge region of the conductive material. The methods may include contacting the edge region of the conductive material with the halogen-containing precursor and the oxygen-containing precursor. The methods may include etching in a first etching operation the edge region of the conductive material to a partial depth through the conductive material to produce a footing of conductive material protruding along the edge region of the conductive material. The methods may also include removing the footing of conductive material in a second etching operation.

公开(公告)号：US10964527B2

公开(公告)日：2021-03-30

申请号：US16401883

申请日：2019-05-02

Applicant: Applied Materials, Inc.

Inventor： Jong Mun Kim ,  Biao Liu ,  Cheng Pan ,  Erica Chen ,  Chentsau Ying ,  Srinivas Nemani ,  Ellie Yieh

IPC: H01L21/02 ,  H01L21/3105 ,  H01L21/311

Abstract: Methods for removing residuals after a selective deposition process are provided. In one embodiment, the method includes performing a selective deposition process to form a metal containing dielectric material at a first location of a substrate and performing a residual removal process to remove residuals from a second location of the substrate.

公开(公告)号：US10957548B2

公开(公告)日：2021-03-23

申请号：US16683828

申请日：2019-11-14

Applicant: APPLIED MATERIALS, INC.

Inventor： Mang-Mang Ling ,  Jong Mun Kim ,  Chentsau Ying

IPC: H01L21/308 ,  H01L21/3065 ,  C09K13/10 ,  C01B19/00 ,  H01L21/67

Abstract: Methods for dry plasma etching thin layers of material including Cu(In, Ga)Se, e.g., CIGS material on semiconductor substrates are provided. A method of etching a CIGS material layer such as copper indium gallium selenide film, includes: flowing an etching gas including a mixture of gases into a process chamber having a substrate disposed therein, the substrate including a copper indium gallium selenide layer having a patterned film stack disposed thereon, the patterned film stack covering a first portion of the copper indium gallium selenide layer and exposing a second portion of the copper indium gallium selenide layer; and contacting the copper indium gallium selenide layer with the etching gas to remove the second portion and form one or more copper indium gallium selenide edges of the first portion.

公开(公告)号：US10916433B2

公开(公告)日：2021-02-09

申请号：US16366539

申请日：2019-03-27

Applicant: Applied Materials, Inc.

Inventor： He Ren ,  Maximillian Clemons ,  Mei-Yee Shek ,  Minrui Yu ,  Bencherki Mebarki ,  Mehul B. Naik ,  Chentsau Ying ,  Srinivas D. Nemani

IPC: H01L21/285 ,  H01L21/32 ,  H01L21/768 ,  C23C14/04 ,  C23C14/06 ,  C23C14/35 ,  C23C14/22 ,  C23C14/58 ,  H01L29/45 ,  H01L21/3205 ,  H01L23/532

Abstract: Methods for forming low resistivity metal silicide interconnects using one or a combination of a physical vapor deposition (PVD) process and an anneal process are described herein. In one embodiment, a method of forming a plurality of wire interconnects includes flowing a sputtering gas into a processing volume of a processing chamber, applying a power to a target disposed in the processing volume, forming a plasma in a region proximate to the sputtering surface of the target, and depositing the metal and silicon layer on the surface of the substrate. Herein, the first target comprises a metal silicon alloy and a sputtering surface thereof is angled with respect to a surface of the substrate at between about 10° and about 50°.

公开(公告)号：US10249495B2

公开(公告)日：2019-04-02

申请号：US15195640

申请日：2016-06-28

Applicant: Applied Materials, Inc.

Inventor： Yang Yang ,  Lucy Chen ,  Jie Zhou ,  Kartik Ramaswamy ,  Kenneth S. Collins ,  Srinivas D. Nemani ,  Chentsau Ying ,  Jingjing Liu ,  Steven Lane ,  Gonzalo Monroy ,  James D. Carducci

IPC: C23C16/26 ,  H01L21/033 ,  C23C16/505 ,  C23C16/509 ,  C23C16/56 ,  H01J37/32 ,  H01L21/02 ,  H01L21/308 ,  H01L21/3213 ,  C01B32/25 ,  H01L21/762

Abstract: Methods for forming a diamond like carbon layer with desired film density, mechanical strength and optical film properties are provided. In one embodiment, a method of forming a diamond like carbon layer includes generating an electron beam plasma above a surface of a substrate disposed in a processing chamber, and forming a diamond like carbon layer on the surface of the substrate. The diamond like carbon layer is formed by an electron beam plasma process, wherein the diamond like carbon layer serves as a hardmask layer in an etching process in semiconductor applications. The diamond like carbon layer may be formed by bombarding a carbon containing electrode disposed in a processing chamber to generate a secondary electron beam in a gas mixture containing carbon to a surface of a substrate disposed in the processing chamber, and forming a diamond like carbon layer on the surface of the substrate from elements of the gas mixture.

公开(公告)号：US20190013250A1

公开(公告)日：2019-01-10

申请号：US16026598

申请日：2018-07-03

Applicant: Applied Materials, Inc.

Inventor： Liyan Miao ,  Chentsau Ying ,  Xinhai Han ,  Long Lin

IPC: H01L21/66 ,  H01L21/02 ,  H01L21/3205 ,  C23C16/52 ,  C23C16/34 ,  C23C16/24 ,  C23C16/40

Abstract: Embodiments of the present technology may include a method of forming a stack of semiconductor layers. The method may include depositing a first silicon oxide layer on a substrate. The method may also include depositing a first silicon layer on the first silicon oxide layer. The method may further include depositing a first silicon nitride layer on the first silicon layer. Depositing the first silicon nitride layer or a stress layer may include reducing stress in at least one of the first silicon layer, the first silicon oxide layer, or the substrate. In addition, the method may include depositing a second silicon layer on the first silicon nitride layer. The operations may form the stack of semiconductor layers, where the stack includes the first silicon oxide layer, the first silicon layer, the first silicon nitride layer, and the second silicon layer.

公开(公告)号：US20180082861A1

公开(公告)日：2018-03-22

申请号：US15828112

申请日：2017-11-30

Applicant: Applied Materials, Inc.

Inventor： Bhargav Citla ,  Chentsau Ying ,  Srinivas Nemani ,  Viachslav Babayan ,  Michael Stowell

IPC: H01L21/67 ,  H01L21/687 ,  H01L21/311 ,  H01L21/3115 ,  H01L21/683

Abstract: Semiconductor systems and methods may include methods of performing selective etches that include modifying a material on a semiconductor substrate. The substrate may have at least two exposed materials on a surface of the semiconductor substrate. The methods may include forming a low-power plasma within a processing chamber housing the semiconductor substrate. The low-power plasma may be a radio-frequency (“RF”) plasma, which may be at least partially formed by an RF bias power operating between about 10 W and about 100 W in embodiments. The RF bias power may also be pulsed at a frequency below about 5,000 Hz. The methods may also include etching one of the at least two exposed materials on the surface of the semiconductor substrate at a higher etch rate than a second of the at least two exposed materials on the surface of the semiconductor substrate.

公开(公告)号：US20180051368A1

公开(公告)日：2018-02-22

申请号：US15600247

申请日：2017-05-19

Applicant: Applied Materials, Inc.

Inventor： Jingjing Liu ,  Zhong Qiang Hua ,  Adolph Miller Allen ,  Michael W. Stowell ,  Srinivas D. Nemani ,  Chentsau Ying ,  Bhargav Citla ,  Viachslav Babayan ,  Andrej Halabica

IPC: C23C14/06 ,  C23C14/35 ,  C23C14/34 ,  C23C14/54 ,  H01J37/34 ,  H01L21/02

CPC classification number: C23C14/0605 ,  C23C14/3485 ,  C23C14/35 ,  C23C14/354 ,  C23C14/541 ,  C23C14/542 ,  H01J37/32724 ,  H01J37/3426 ,  H01J37/3435 ,  H01J37/3452 ,  H01J37/3467 ,  H01L21/02115 ,  H01L21/02266 ,  H01L21/0332 ,  H01L21/31144

Abstract: A deposited amorphous carbon film includes at least 95% carbon. A percentage of sp3 carbon-carbon bonds present in the amorphous carbon film exceeds 30%, and a hydrogen content of the amorphous carbon film is less than 5%. A process of depositing amorphous carbon on a workpiece includes positioning the workpiece within a process chamber and positioning a magnetron assembly adjacent to the process chamber. The magnetron assembly projects a magnetic field into the process chamber. The method further includes providing a carbon target such that the magnetic field extends through the carbon target toward the workpiece. The method further includes providing a source gas to the process chamber, and providing pulses of DC power to a plasma formed from the source gas within the process chamber. The pulses of DC power are supplied in pulses of 40 microseconds or less, that repeat at a frequency of at least 4 kHz.

公开(公告)号：US09484202B1

公开(公告)日：2016-11-01

申请号：US14729932

申请日：2015-06-03

Applicant: Applied Materials, Inc.

Inventor： Jie Zhou ,  Chentsau Ying ,  Shambhu N. Roy ,  Srinivas D. Nemani ,  Jingjing Liu ,  Ellie Y. Yieh

IPC: H01L21/302 ,  H01L21/033 ,  H01L21/311

CPC classification number: H01L21/311 ,  H01L21/0337

Abstract: Embodiments herein provide apparatus and methods for performing a deposition and a patterning process on a spacer layer with good profile control in multiple patterning processes. In one embodiment, a method for depositing and patterning a spacer layer during a multiple patterning process includes conformally forming a spacer layer on an outer surface of a patterned structure disposed on a substrate, wherein the patterned structure has a first group of openings defined therebetween, selectively treating a first portion of the spacer layer formed on the substrate without treating a second portion of the spacer layer, and selectively removing the treated first portion of the spacer layer.

Abstract translation: 本文的实施例提供了用于在多个图案化工艺中对具有良好轮廓控制的间隔层执行沉积和图案化工艺的装置和方法。 在一个实施例中，在多次图案化工艺期间用于沉积和图案化间隔层的方法包括在设置在衬底上的图案化结构的外表面上共形形成间隔层，其中图案化结构具有限定在其间的第一组开口， 选择性地处理形成在衬底上的间隔层的第一部分，而不处理间隔层的第二部分，并且选择性地去除间隔层的经处理的第一部分。

公开(公告)号：US20200091019A1

公开(公告)日：2020-03-19

申请号：US16688811

申请日：2019-11-19

Applicant: Applied Materials, Inc.

Inventor： Liyan Miao ,  Chentsau Ying ,  Xinhai Han ,  Long Lin

IPC: H01L21/66 ,  H01L21/02 ,  H01L21/3205 ,  C23C16/40 ,  C23C16/52 ,  C23C16/34 ,  C23C16/24 ,  C23C16/452 ,  H01J37/32 ,  H01L51/00 ,  C23C16/54 ,  H01L21/683 ,  C23C16/455 ,  C23C16/509

Abstract: Embodiments of the present technology may include a method of forming a stack of semiconductor layers. The method may include depositing a first silicon oxide layer on a substrate. The method may also include depositing a first silicon layer on the first silicon oxide layer. The method may include depositing a first silicon nitride layer on the first silicon layer. The method may further include depositing a second silicon layer on the first silicon nitride layer. In addition, the method may include depositing a stress layer on a side of the substrate opposite a side of the substrate with the first silicon oxide layer. The operations may form a structure of semiconductor layers, where the structure includes the first silicon oxide layer, the first silicon layer, the first silicon nitride layer, the second silicon layer, the substrate, and the stress layer. Other methods of reducing stress are described.