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公开(公告)号：US11837582B2
公开(公告)日：2023-12-05
申请号：US18148327
申请日：2022-12-29
Inventor： Guilian Gao , Cyprian Emeka Uzoh , Jeremy Alfred Theil , Belgacem Haba , Rajesh Katkar
IPC: H01L25/065 , H01L21/768 , H01L23/538 , H01L23/00
CPC classification number: H01L25/0657 , H01L21/76898 , H01L23/5384 , H01L23/5385 , H01L23/5386 , H01L24/95
Abstract: Dies and/or wafers are stacked and bonded in various arrangements including stacks, and may be covered with a molding to facilitate handling, packaging, and the like. In various examples, the molding may cover more or less of a stack, to facilitate connectivity with the devices of the stack, to enhance thermal management, and so forth.
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12.发明授权公开(公告)号：US11817409B2
公开(公告)日：2023-11-14
申请号：US17563506
申请日：2021-12-28
Inventor： Belgacem Haba , Rajesh Katkar , Ilyas Mohammed , Javier A. DeLaCruz
CPC classification number: H01L24/08 , H01L21/78 , H01L24/80 , H01L24/94 , H01L2224/08146 , H01L2224/80006 , H01L2224/80895 , H01L2224/80896
Abstract: A bonded structure can include a first reconstituted element comprising a first element and having a first side comprising a first bonding surface and a second side opposite the first side. The first reconstituted element can comprise a first protective material disposed about a first sidewall surface of the first element. The bonded structure can comprise a second reconstituted element comprising a second element and having a first side comprising a second bonding surface and a second side opposite the first side. The first reconstituted element can comprise a second protective material disposed about a second sidewall surface of the second element. The second bonding surface of the first side of the second reconstituted element can be directly bonded to the first bonding surface of the first side of the first reconstituted element without an intervening adhesive along a bonding interface.
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公开(公告)号：US11762200B2
公开(公告)日：2023-09-19
申请号：US17124408
申请日：2020-12-16
Inventor： Rajesh Katkar , Belgacem Haba
IPC: G02B27/01 , G02B27/14 , H01L25/07 , G02B27/10 , H01L25/075
CPC classification number: G02B27/0172 , G02B27/102 , G02B27/141 , H01L25/0753 , G02B2027/0178
Abstract: A bonded optical device is disclosed. The bonded optical device can include a first optical element, a second optical element, and an optical pathway. The first optical element has a first array of optical emitters configured to emit light of a first color. The first optical element is bonded to at least one processor element, the at least one processor element including active circuitry configured to control operation of the first optical element. The second optical element has a second array of optical emitters configured to emit light of a second color different from the first color. The second optical element is bonded to the at least one processor element. The optical pathway is optically coupled with the first and second optical elements. The optical pathway is configured to transmit a superposition of light from the first and second optical emitters to an optical output to be viewed by users.
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公开(公告)号：US20230197560A1
公开(公告)日：2023-06-22
申请号：US18067668
申请日：2022-12-16
Inventor： Rajesh Katkar , Belgacem Haba
CPC classification number: H01L23/38 , H01L24/08 , H01L2224/08245 , H01L2924/351
Abstract: In some aspects, the disclosed technology provides microelectronic devices which can effectively dissipate heat and manage hot spot. In some embodiments, a disclosed microelectronic device may include a substrate having a thickness in a first direction and at least one thermoelectric unit disposed in or on the substrate. The thermoelectric unit may be configured to transfer heat along a second lateral direction orthogonal to the first direction.
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公开(公告)号：US11670615B2
公开(公告)日：2023-06-06
申请号：US17131588
申请日：2020-12-22
Inventor： Liang Wang , Rajesh Katkar , Javier A. DeLaCruz , Arkalgud R. Sitaram
IPC: H01L23/00 , H01L23/498 , H01L23/532 , H01L23/528 , H01L23/10 , B81C1/00 , H05K1/11
CPC classification number: H01L24/29 , B81C1/00269 , B81C1/00293 , H01L23/10 , H01L23/49838 , H01L23/528 , H01L23/53228 , H01L23/53242 , H01L24/05 , H01L24/06 , H01L24/08 , B81B2207/012 , B81C2203/035 , H01L23/562 , H01L24/80 , H01L2224/05551 , H01L2224/05552 , H01L2224/05555 , H01L2224/05571 , H01L2224/05647 , H01L2224/05686 , H01L2224/06135 , H01L2224/06155 , H01L2224/06165 , H01L2224/06505 , H01L2224/08121 , H01L2224/08237 , H01L2224/29019 , H01L2224/8001 , H01L2224/80047 , H01L2224/80895 , H01L2224/80896 , H01L2224/80948 , H05K1/111 , H01L2224/05552 , H01L2924/00012 , H01L2224/05647 , H01L2924/00014 , H01L2224/05686 , H01L2924/053
Abstract: A bonded structure can include a first element having a first conductive interface feature and a second element having a second conductive interface feature. An integrated device can be coupled to or formed with the first element or the second element. The first conductive interface feature can be directly bonded to the second conductive interface feature to define an interface structure. The interface structure can be disposed about the integrated device in an at least partially annular profile to connect the first and second elements.
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Patent Agency Ranking
公开(公告)号：US20230123423A1
公开(公告)日：2023-04-20
申请号：US18047238
申请日：2022-10-17
Applicant: ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC
Inventor： Guilian Gao , Gaius Gillman Fountain, Jr. , Belgacem Haba , Rajesh Katkar
IPC: H01L23/522 , H01L25/065 , H01L23/00 , H01L23/48
Abstract: Microelectronic devices having stacked electromagnetic coils are disclosed. In one example, a microelectronic device can include a first semiconductor element and a second semiconductor element disposed on the first semiconductor element. The microelectronic device can also include an electromagnetic coil. A first portion of the electromagnetic coil and a second portion of the electromagnetic coil may be spaced apart by the first semiconductor element. A first conductive via extending through the first semiconductor element may connect the first and second portions of the electromagnetic coil. Methods for forming such microelectronic devices are also disclosed.
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17.发明授权公开(公告)号：US12191235B2
公开(公告)日：2025-01-07
申请号：US18512567
申请日：2023-11-17
Inventor： Belgacem Haba , Rajesh Katkar
IPC: H01L23/473 , H01L23/00 , H01L23/427 , H01L23/498 , H01L25/18 , H10B80/00
Abstract: The present disclosure provides for integrated cooling systems including an integrated cooling assembly. The integrated cooling assembly includes a semiconductor device having an active side and a backside opposite the active side. The integrated cooling assembly includes a plurality of stacked and bonded layers that collectively form a cold plate, the cold plate comprising (i) a first side and a second side opposite the first side, the first side having a base surface, a support feature that extends downwardly from the base surface, and sidewalls that extend downwardly from the base surface and surround base surface and the support feature, and (ii) a first interconnect vertically disposed through the support feature, where the first interconnect is electrically coupled to the semiconductor device through direct hybrid bonds formed between the cold plate and the semiconductor device.
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公开(公告)号：US20250006674A1
公开(公告)日：2025-01-02
申请号：US18497585
申请日：2023-10-30
Inventor： Cyprian Emeka Uzoh , Oliver Zhao , Gabriel Z. Guevara , Dominik Suwito , Rajesh Katkar
IPC: H01L23/00
Abstract: A semiconductor element is provided with a micro-structured metal layer over conductive features of a hybrid bonding surface. The micro-structured metal layer comprises fine metal grain microstructure, such as nanograins. The micro-structured metal layer can be formed over the conductive features by providing a metal oxide and reducing the metal oxide to metal. The micro-structured metal layer can be formed selectively if the metal oxide is formed by oxidation. When directly bonded to another element, the micro-structured metal layer forming strong bonds at the bonding interface can substantially reduce annealing temperature.
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公开(公告)号：US12176303B2
公开(公告)日：2024-12-24
申请号：US18346396
申请日：2023-07-03
Inventor： Javier A. DeLaCruz , Rajesh Katkar
IPC: H01L23/00
Abstract: A bonded structure is disclosed. The bonded structure can include a semiconductor element comprising active circuitry. The bonded structure can include an obstructive element bonded to the semiconductor element along a bond interface, the obstructive element including an obstructive material disposed over the active circuitry, the obstructive material configured to obstruct external access to the active circuitry. The bonded element can include an artifact structure indicative of a wafer-level bond in which the semiconductor element and the obstructive element formed part of respective wafers directly bonded prior to singulation.
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20.发明授权公开(公告)号：US12176263B2
公开(公告)日：2024-12-24
申请号：US18620753
申请日：2024-03-28
Applicant: Adeia Semiconductor Bonding Technologies Inc
Inventor： Belgacem Haba , Cyprian Emeka Uzoh , Rajesh Katkar
IPC: H01L23/46 , H01L23/00 , H01L23/34 , H01L23/373 , H01L23/48 , H01L23/498 , H01L23/24
Abstract: The present disclosure provides for integrated cooling systems including backside power delivery and methods of manufacturing the same. An integrated cooling assembly may include a device and a cold plate. The cold plate has a first side and an opposite second side, the first side having a recessed surface, sidewalls around the recessed surface that extend downwardly therefrom to define a cavity, and a plurality of support features disposed in the cavity. The first side of the cold plate is attached to a backside of the device to define a coolant channel therebetween. The cold plate includes a substrate, a dielectric layer disposed on a first surface of the substrate, a first conductive layer disposed between the first surface and the dielectric layer, a second conductive layer disposed on a second surface of the substrate, and thru-substrate interconnects connecting the first conductive layer to the second conductive layer.
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