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    HYBRID SOLID-STATE MEMORY SYSTEM HAVING VOLATILE AND NON-VOLATILE MEMORY
    11.
    发明申请
    HYBRID SOLID-STATE MEMORY SYSTEM HAVING VOLATILE AND NON-VOLATILE MEMORY 审中-公开
    具有挥发性和非易失性存储器的混合固态存储器系统

    公开(公告)号：US20140185379A1

    公开(公告)日：2014-07-03

    申请号：US14197505

    申请日：2014-03-05

    申请人： MOSAID TECHNOLOGIES INCORPORATED

    发明人： Jin-Ki KIM

    IPC分类号： G11C14/00

    CPC分类号： G11C14/0018 ,  G11C11/005

    摘要： A hybrid solid-state memory system is provided for storing data. The solid-state memory system comprises a volatile solid-state memory, a non-volatile solid-state memory, and a memory controller. Further, a method is provided for storing data in the solid-state memory system. The method comprises the following steps. A write command is received by the memory controller. Write data is stored in the volatile memory in response to the write command. Data is transferred from the volatile memory to the non-volatile memory in response to a data transfer request.

    摘要翻译： 提供了用于存储数据的混合固态存储器系统。 固态存储器系统包括易失性固态存储器，非易失性固态存储器和存储器控制器。 此外，提供了一种用于将数据存储在固态存储器系统中的方法。 该方法包括以下步骤。 存储器控制器接收写命令。 响应于写命令，写数据存储在易失性存储器中。 响应于数据传输请求，数据从易失性存储器传送到非易失性存储器。

    PACKET DATA ID GENERATION FOR SERIALLY INTERCONNECTED DEVICES
    12.
    发明申请
    PACKET DATA ID GENERATION FOR SERIALLY INTERCONNECTED DEVICES 审中-公开
    用于串行互连设备的分组数据ID生成

    公开(公告)号：US20140173322A1

    公开(公告)日：2014-06-19

    申请号：US14185401

    申请日：2014-02-20

    申请人： MOSAID TECHNOLOGIES INCORPORATED

    发明人： Hong Beom PYEON ,  HakJune OH

    IPC分类号： G06F1/12

    CPC分类号： G06F1/12 ,  G06F1/04 ,  G11C5/00 ,  G11C5/066 ,  G11C7/20

    摘要： Various memory devices (e.g., DRAMs, flash memories) are serially interconnected. The memory devices need their identifiers (IDs). Each of the memory devices generates IDs for neighboring memory devices. The IDs are generated synchronously with clock. Command data and previously generated ID data are synchronously registered. The registered data is synchronously output and provided as parallel data for calculation of a new ID for the neighboring device. The calculation is an addition or subtraction by one. The IDs are generated in a packet basis by interpreting serial packet-basis commands received at the serial input in response to clocks. A clock latency is controlled in response to the interpreted ID and the clock. In accordance with the controlled clock latency, a new ID is provided in a packet basis. In high frequency generation applications (e.g., 1 GHz), two adjacent devices connected in daisy chain fashion are guaranteed enough time margin to perform the interpretation of packet commands.

    摘要翻译： 各种存储器件（例如，DRAM，闪存）串联连接。 存储器件需要它们的标识符（ID）。 每个存储器件产生相邻存储器件的ID。 ID与时钟同步生成。 命令数据和先前生成的ID数据被同步地注册。 注册的数据被同步输出并作为用于计算相邻设备的新ID的并行数据提供。 计算是一个加法或减法。 通过解释响应于时钟在串行输入端接收的基于串行数据包的命令，以分组的形式生成ID。 响应于解释的ID和时钟来控制时钟延迟。 根据受控时钟延迟，以分组为基础提供新的ID。 在高频产生应用（例如，1GHz）中，以菊链方式连接的两个相邻设备保证足够的时间余量来执行分组命令的解释。

    MEMORY WITH OUTPUT CONTROL
    14.
    发明申请
    MEMORY WITH OUTPUT CONTROL 有权
    带输出控制的存储器

    公开(公告)号：US20140133242A1

    公开(公告)日：2014-05-15

    申请号：US14156047

    申请日：2014-01-15

    申请人： MOSAID Technologies Incorporated

    发明人： HakJune OH ,  Hong Beom PYEON ,  Jin-Ki KIM

    IPC分类号： G11C16/26

    CPC分类号： G11C11/5628 ,  G06F1/12 ,  G11C7/1021 ,  G11C7/1051 ,  G11C7/1078 ,  G11C11/5642 ,  G11C16/06 ,  G11C16/10 ,  G11C16/16 ,  G11C16/26 ,  G11C16/3445 ,  G11C2207/107

    摘要： An apparatus, system, and method for controlling data transfer to an output port of a serial data link interface in a semiconductor memory is disclosed. In one example, a flash memory device may have multiple serial data links, multiple memory banks and control input ports that enable the memory device to transfer the serial data to a serial data output port of the memory device. In another example, a flash memory device may have a single serial data link, a single memory bank, a serial data input port, a control input port for receiving output enable signals. The flash memory devices may be cascaded in a daisy-chain configuration using echo signal lines to serially communicate between memory devices.

    摘要翻译： 公开了一种用于控制向半导体存储器中的串行数据链路接口的输出端口传送数据的装置，系统和方法。 在一个示例中，闪存设备可以具有多个串行数据链路，多个存储器组和控制输入端口，其使得存储器设备能够将串行数据传送到存储器件的串行数据输出端口。 在另一示例中，闪存器件可以具有单个串行数据链路，单个存储体，串行数据输入端口，用于接收输出使能信号的控制输入端口。 闪存器件可以使用回波信号线以菊花链配置级联以在存储器件之间串行通信。

    HIERARCHICAL COMMON SOURCE LINE STRUCTURE IN NAND FLASH MEMORY
    15.
    发明申请
    HIERARCHICAL COMMON SOURCE LINE STRUCTURE IN NAND FLASH MEMORY 审中-公开
    NAND FLASH存储器中的分层通用源结构

    公开(公告)号：US20140133236A1

    公开(公告)日：2014-05-15

    申请号：US14159823

    申请日：2014-01-21

    申请人： MOSAID Technologies Incorporated

    发明人： Hong Beom PYEON ,  Jin-Ki KIM

    IPC分类号： G11C16/34

    CPC分类号： G11C16/3427 ,  G11C16/0483 ,  G11C16/12 ,  G11C16/30

    摘要： Each memory cell string in a generic NAND flash cell block connects to a Common Source Line (CLS). A value for applying to the CSL is centrally generated and distributed to a local switch logic unit corresponding to each NAND flash cell block. For source-line page programming, the distribution line may be called a Global Common Source Line (GCSL). In an array of NAND flash cell blocks, only one NAND flash cell block is selected at a time for programming. To reduce power consumption, only the selected NAND flash cell block receives a value on the CSL that is indicative of the value on the GCSL. Additionally, the CSLs of non-selected NAND flash cell blocks may be disabled through an active connection to ground.

    摘要翻译： 通用NAND闪存单元块中的每个存储单元串连接到公共源线（CLS）。 集中生成用于应用于CSL的值并将其分配给对应于每个NAND闪存单元块的本地开关逻辑单元。 对于源行页面编程，分发线可以称为全局公用源线（GCSL）。 在NAND闪存单元块的阵列中，一次仅选择一个NAND闪存单元块进行编程。 为了降低功耗，只有选定的NAND闪存单元块才接收到指示GCSL上的值的CSL上的值。 此外，未选择的NAND闪存单元块的CSL可以通过主动连接到地来禁用。

    METHOD AND SYSTEM FOR PACKET PROCESSING
    16.
    发明申请
    METHOD AND SYSTEM FOR PACKET PROCESSING 有权
    分组处理方法与系统

    公开(公告)号：US20140122582A1

    公开(公告)日：2014-05-01

    申请号：US14148895

    申请日：2014-01-07

    申请人： MOSAID TECHNOLOGIES INCORPORATED

    发明人： Arthur John LOW ,  Stephen J. DAVIS

    IPC分类号： H04L29/06

    CPC分类号： H04L67/42 ,  H04L49/90 ,  H04L49/9036 ,  H04L63/0428 ,  H04L63/0485 ,  H04L67/34 ,  H04L69/22 ,  H04L69/329

    摘要： A data processor and a method for processing data is disclosed. The processor has an input port for receiving packets of data to be processed. A master controller acts to analyse the packets and to provide a header including a list of processes to perform on the packet of data and an ordering thereof. The master controller is programmed with process related data relating to the overall processing function of the processor. The header is appended to the packet of data. The packet with the appended header information is stored within a buffer. A buffer controller acts to determine for each packet stored within the buffer based on the header within the packet a next processor to process the packet. The controller then provides the packet to the determined processor for processing. The processed packet is returned with some indication that the processing is done. For example, the process may be deleted from the list of processes. The buffer controller repeatedly makes a determination of a next process until there is no next process for a packet at which time it is provided to an output port.

    摘要翻译： 公开了一种用于处理数据的数据处理器和方法。 处理器具有用于接收待处理数据的数据包的输入端口。 主控制器用于分析分组并提供包括要在数据分组上执行的进程列表及其排序的报头。 主控制器被编程有与处理器的整体处理功能相关的过程相关数据。 标题附加到数据包。 具有附加标题信息的分组被存储在缓冲器中。 缓冲器控制器用于基于分组内的报头来确定存储在缓冲器内的每个分组，以处理分组的下一个处理器。 然后，控制器将该分组提供给所确定的处理器进行处理。 返回处理后的数据包，表示处理完成。 例如，可以从进程列表中删除该进程。 缓冲器控制器重复地进行下一个处理的确定，直到在其被提供给输出端口的分组没有下一个处理为止。

    Semiconductor Memory Asynchronous Pipeline
    17.
    发明申请
    Semiconductor Memory Asynchronous Pipeline 有权
    半导体存储器异步管道

    公开(公告)号：US20140089575A1

    公开(公告)日：2014-03-27

    申请号：US14089242

    申请日：2013-11-25

    申请人： MOSAID Technologies Incorporated

    发明人： Ian Mes

    IPC分类号： G11C7/10

    CPC分类号： G11C7/1072 ,  G11C7/1039 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/22 ,  G11C7/222 ,  G11C11/4076

    摘要： An asynchronously pipelined SDRAM has separate pipeline stages that are controlled by asynchronous signals. Rather than using a clock signal to synchronize data at each stage, an asynchronous signal is used to latch data at every stage. The asynchronous control signals are generated within the chip and are optimized to the different latency stages. Longer latency stages require larger delays elements, while shorter latency states require shorter delay elements. The data is synchronized to the clock at the end of the read data path before being read out of the chip. Because the data has been latched at each pipeline stage, it suffers from less skew than would be seen in a conventional wave pipeline architecture. Furthermore, since the stages are independent of the system clock, the read data path can be run at any CAS latency as long as the re-synchronizing output is built to support it.

    摘要翻译： 异步流水线SDRAM具有由异步信号控制的单独流水线级。 不是使用时钟信号在每个阶段同步数据，而是使用异步信号来锁存每个阶段的数据。 异步控制信号在芯片内产生，并针对不同的延迟级进行了优化。 更长的延迟阶段需要更大的延迟元件，而较短的等待时间状态需要更短的延迟元件。 在从芯片读出之前，数据与读取数据路径末端的时钟同步。 由于数据已经在每个流水线阶段被锁存，所以它比在传统的波浪管线架构中看到的偏差更小。 此外，由于这些阶段与系统时钟无关，只要构建重新同步输出以支持读取数据路径，就可以以任何CAS延迟运行。

    Memory with output control
    19.
    发明授权
    Memory with output control 有权
    内存带输出控制

    公开(公告)号：US08654601B2

    公开(公告)日：2014-02-18

    申请号：US13867437

    申请日：2013-04-22

    申请人： Mosaid Technologies Incorporated

    发明人： HakJune Oh ,  Hong Beom Pyeon ,  Jin-Ki Kim

    IPC分类号： G11C7/00

    CPC分类号： G11C11/5628 ,  G06F1/12 ,  G11C7/1021 ,  G11C7/1051 ,  G11C7/1078 ,  G11C11/5642 ,  G11C16/06 ,  G11C16/10 ,  G11C16/16 ,  G11C16/26 ,  G11C16/3445 ,  G11C2207/107

    摘要： An apparatus, system, and method for controlling data transfer to an output port of a serial data link interface in a semiconductor memory is disclosed. In one example, a flash memory device may have multiple serial data links, multiple memory banks and control input ports that enable the memory device to transfer the serial data to a serial data output port of the memory device. In another example, a flash memory device may have a single serial data link, a single memory bank, a serial data input port, a control input port for receiving output enable signals. The flash memory devices may be cascaded in a daisy-chain configuration using echo signal lines to serially communicate between memory devices.

    摘要翻译： 公开了一种用于控制向半导体存储器中的串行数据链路接口的输出端口传送数据的装置，系统和方法。 在一个示例中，闪存设备可以具有多个串行数据链路，多个存储器组和控制输入端口，其使得存储器设备能够将串行数据传送到存储器件的串行数据输出端口。 在另一示例中，闪存器件可以具有单个串行数据链路，单个存储体，串行数据输入端口，用于接收输出使能信号的控制输入端口。 闪存器件可以使用回波信号线以菊花链配置级联以在存储器件之间串行通信。

    SYSTEM FOR TRANSMISSION LINE TERMINATION BY SIGNAL CANCELLATION
    20.
    发明申请
    SYSTEM FOR TRANSMISSION LINE TERMINATION BY SIGNAL CANCELLATION 审中-公开
    通过信号取消传输线路终端的系统

    公开(公告)号：US20140035615A1

    公开(公告)日：2014-02-06

    申请号：US14053828

    申请日：2013-10-15

    申请人： MOSAID Technologies Incorporated

    发明人： Yehuda Binder

    IPC分类号： H03K19/00

    CPC分类号： H03K19/0005 ,  H04L5/14 ,  H04L12/40032 ,  H04L25/02 ,  H04L25/0272 ,  H04L25/0298 ,  H04L27/00 ,  H04L27/0002

    摘要： A communication system having first and second states for use with a shared transmission line composed of at least two conductors and composed of first and second transmission line segments connected to each other at a single connection point. In the first state, a termination is coupled to the single connection point and is operative to at least attenuate a signal propagated between the first and second segments. In the second state, a driver is coupled to the connection point and is operative to conduct a signal over the first and second segments.

    摘要翻译： 一种具有第一和第二状态的通信系统，其用于由至少两个导体组成的共享传输线，并且由在单个连接点处彼此连接的第一和第二传输线段组成。 在第一状态中，终端耦合到单个连接点，并且可操作以至少衰减在第一和第二段之间传播的信号。 在第二状态下，驱动器耦合到连接点，并且可操作以在第一和第二段上传导信号。