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    Integration of fin-based devices and ETSOI devices
    11.
    发明授权
    Integration of fin-based devices and ETSOI devices 有权
    集成了鳍式设备和ETSOI设备

    公开(公告)号：US08779511B2

    公开(公告)日：2014-07-15

    申请号：US13530887

    申请日：2012-06-22

    Applicant: Narasimhulu Kanike ,  Kangguo Cheng ,  Ramachandra Divakaruni ,  Carl J. Radens

    Inventor： Narasimhulu Kanike ,  Kangguo Cheng ,  Ramachandra Divakaruni ,  Carl J. Radens

    IPC: H01L27/088

    CPC classification number: H01L27/1211 ,  H01L21/845

    Abstract: Thin semiconductor regions and thick semiconductor regions are formed oven an insulator layer. Thick semiconductor regions include at least one semiconductor fin. A gate conductor layer is patterned to form disposable planar gate electrodes over ETSOI regions and disposable side gate electrodes on sidewalls of semiconductor fins. End portions of the semiconductor fins are vertically recessed to provide thinned fin portions adjacent to an unthinned fin center portion. After appropriate masking by dielectric layers, selective epitaxy is performed on planar source and drain regions of ETSOI field effect transistors (FETs) to form raised source and drain regions. Further, fin source and drain regions are grown on the thinned fin portions. Source and drain regions, fins, and the disposable gate electrodes are planarized. The disposable gate electrodes are replaced with metal gate electrodes. FinFETs and ETSOI FETs are provided on the same semiconductor substrate.

    Abstract translation: 薄半导体区域和厚半导体区域被形成为绝缘体层。 厚半导体区域包括至少一个半导体鳍片。 图案化栅极导体层以在半导体鳍片的侧壁上的ETSOI区域和一次侧栅电极上形成一次性平面栅电极。 半导体翅片的端部垂直凹入，以提供与未固定的翅片中心部分相邻的变薄的翅片部分。 在通过介电层适当掩蔽之后，在ETSOI场效应晶体管（FET）的平面源极和漏极区域上进行选择性外延以形成升高的源极和漏极区域。 此外，翅片源极和漏极区域在薄的鳍部上生长。 源极和漏极区域，鳍片和一次性栅电极被平坦化。 一次性栅电极被金属栅电极代替。 FinFET和ETSOI FET设置在相同的半导体衬底上。

    Implant free extremely thin semiconductor devices
    12.
    发明授权
    Implant free extremely thin semiconductor devices 有权
    植入物非常薄的半导体器件

    公开(公告)号：US08710588B2

    公开(公告)日：2014-04-29

    申请号：US13595025

    申请日：2012-08-27

    Applicant: Kangguo Cheng ,  Bruce B. Doris ,  Dechao Guo ,  Pranita Kulkarni ,  Philip J. Oldiges ,  Ghavam G. Shahidi

    Inventor： Kangguo Cheng ,  Bruce B. Doris ,  Dechao Guo ,  Pranita Kulkarni ,  Philip J. Oldiges ,  Ghavam G. Shahidi

    IPC: H01L27/12

    CPC classification number: H01L29/66636 ,  H01L29/66772 ,  H01L29/78621 ,  H01L29/78654

    Abstract: A semiconductor device and a method of fabricating a semiconductor device are disclosed. In one embodiment, the method comprises providing a semiconductor substrate, epitaxially growing a Ge layer on the substrate, and epitaxially growing a semiconductor layer on the Ge layer, where the semiconductor layer has a thickness of 10 nm or less. This method further comprises removing at least a portion of the Ge layer to form a void beneath the Si layer, and filling the void at least partially with a dielectric material. In this way, the semiconductor layer becomes an extremely thin semiconductor-on-insulator layer. In one embodiment, after the void is filled with the dielectric material, in-situ doped source and drain regions are grown on the semiconductor layer. In one embodiment, the method further comprises annealing said source and drain regions to form doped extension regions in the semiconductor layer.

    Abstract translation: 公开了半导体器件和制造半导体器件的方法。 在一个实施例中，该方法包括提供半导体衬底，在衬底上外延生长Ge层，并在Ge层上外延生长半导体层，其中半导体层的厚度为10nm或更小。 该方法还包括去除Ge层的至少一部分以在Si层下形成空隙，并且至少部分地用电介质材料填充空隙。 以这种方式，半导体层成为非常薄的绝缘体上半导体层。 在一个实施例中，在空隙填充有电介质材料之后，在半导体层上生长原位掺杂的源极和漏极区。 在一个实施例中，该方法还包括退火所述源区和漏区以在半导体层中形成掺杂的延伸区。

    SUBLITHOGRAPHIC WIDTH FINFET EMPLOYING SOLID PHASE EPITAXY
    15.
    发明申请
    SUBLITHOGRAPHIC WIDTH FINFET EMPLOYING SOLID PHASE EPITAXY 有权
    使用固体相外延片的子图形宽度FINFET

    公开(公告)号：US20140061793A1

    公开(公告)日：2014-03-06

    申请号：US13597752

    申请日：2012-08-29

    Applicant: Chengwen Pei ,  Kangguo Cheng ,  Joseph Ervin ,  Juntao Li ,  Ravi M. Todi ,  Geng Wang

    Inventor： Chengwen Pei ,  Kangguo Cheng ,  Joseph Ervin ,  Juntao Li ,  Ravi M. Todi ,  Geng Wang

    IPC: H01L27/12 ,  H01L29/06 ,  H01L21/336

    CPC classification number: H01L27/0886 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/0653 ,  H01L29/0657 ,  H01L29/0692 ,  H01L29/66795

    Abstract: A dielectric mandrel structure is formed on a single crystalline semiconductor layer. An amorphous semiconductor material layer is deposited on the physically exposed surfaces of the single crystalline semiconductor layer and surfaces of the mandrel structure. Optionally, the amorphous semiconductor material layer can be implanted with at least one different semiconductor material. Solid phase epitaxy is performed on the amorphous semiconductor material layer employing the single crystalline semiconductor layer as a seed layer, thereby forming an epitaxial semiconductor material layer with uniform thickness. Remaining portions of the epitaxial semiconductor material layer are single crystalline semiconductor fins and thickness of these fins are sublithographic. After removal of the dielectric mandrel structure, the single crystalline semiconductor fins can be employed to form a semiconductor device.

    Abstract translation: 介电心轴结构形成在单晶半导体层上。 非晶半导体材料层沉积在单晶半导体层的物理暴露表面和心轴结构的表面上。 可选地，非晶半导体材料层可以注入至少一种不同的半导体材料。 在采用单晶半导体层作为种子层的非晶半导体材料层上进行固相外延，从而形成厚度均匀的外延半导体材料层。 外延半导体材料层的剩余部分是单晶半导体鳍片，并且这些鳍片的厚度是亚光刻的。 在去除介电心轴结构之后，可以采用单晶半导体鳍形成半导体器件。

    Integrated circuit including DRAM and SRAM/logic
    16.
    发明授权
    Integrated circuit including DRAM and SRAM/logic 有权
    集成电路包括DRAM和SRAM /逻辑

    公开(公告)号：US08653596B2

    公开(公告)日：2014-02-18

    申请号：US13344885

    申请日：2012-01-06

    Applicant: Kangguo Cheng ,  Bruce B. Doris ,  Terence B. Hook ,  Ali Khakifirooz ,  Pranita Kulkarni

    Inventor： Kangguo Cheng ,  Bruce B. Doris ,  Terence B. Hook ,  Ali Khakifirooz ,  Pranita Kulkarni

    IPC: H01L21/70 ,  H01L27/12 ,  H01L21/762 ,  H01L21/84

    CPC classification number: H01L29/945 ,  H01L21/84 ,  H01L27/1052 ,  H01L27/1087 ,  H01L27/10873 ,  H01L27/10894 ,  H01L27/1116 ,  H01L27/1203 ,  H01L27/1207

    Abstract: An integrated circuit includes an SOI substrate with a unitary N+ layer below the BOX, a P region in the N+ layer, an eDRAM with an N+ plate, and logic/SRAM devices above the P region. The P region functions as a back gate of the logic/SRAM devices. An optional intrinsic (undoped) layer can be formed between the P back gate layer and the N+ layer to reduce the junction field and lower the junction leakage between the P back gate and the N+ layer. In another embodiment an N or N+ back gate can be formed in the P region. The N+ back gate functions as a second back gate of the logic/SRAM devices. The N+ plate of the SOI eDRAM, the P back gate, and the N+ back gate can be electrically biased at the same or different voltage potentials. Methods to fabricate the integrated circuits are also disclosed.

    Abstract translation: 集成电路包括在BOX下方具有单一N +层的SOI衬底，N +层中的P区，N +板的eDRAM和P区上方的逻辑/ SRAM器件。 P区域用作逻辑/ SRAM器件的后门。 可以在P背栅层和N +层之间形成可选的本征（未掺杂）层，以减少结场并降低P背栅与N +层之间的结泄漏。 在另一个实施例中，可以在P区中形成N或N +背栅。 N +后门作为逻辑/ SRAM器件的第二个后门。 SOI eDRAM的N +板，P背栅极和N +背栅极可以在相同或不同的电压电位下被电偏置。 还公开了制造集成电路的方法。

    INTEGRATED CIRCUIT HAVING A REPLACEMENT GATE STRUCTURE AND METHOD FOR FABRICATING THE SAME
    18.
    发明申请
    INTEGRATED CIRCUIT HAVING A REPLACEMENT GATE STRUCTURE AND METHOD FOR FABRICATING THE SAME 有权
    具有替代盖结构的集成电路及其制造方法

    公开(公告)号：US20140035010A1

    公开(公告)日：2014-02-06

    申请号：US13562659

    申请日：2012-07-31

    Applicant: Xiuyu Cai ,  Ruilong Xie ,  Kangguo Cheng ,  Ali Khakifirooz

    Inventor： Xiuyu Cai ,  Ruilong Xie ,  Kangguo Cheng ,  Ali Khakifirooz

    IPC: H01L29/772 ,  H01L21/283

    CPC classification number: H01L21/76834 ,  H01L21/28518 ,  H01L21/76897 ,  H01L29/165 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/7834

    Abstract: A method for fabricating an integrated circuit includes forming a temporary gate structure on a semiconductor substrate. The temporary gate structure includes a temporary gate material disposed between two spacer structures. The method further includes forming a first directional silicon nitride liner overlying the temporary gate structure and the semiconductor substrate, etching the first directional silicon nitride liner overlying the temporary gate structure and the temporary gate material to form a trench between the spacer structures, while leaving the directional silicon nitride liner overlying the semiconductor substrate in place, and forming a replacement metal gate structure in the trench. An integrated circuit includes a replacement metal gate structure overlying a semiconductor substrate, a silicide region overlying the semiconductor substrate and positioned adjacent the replacement gate structure; a directional silicon nitride liner overlying a portion of the replacement gate structure; and a contact plug in electrical communication with the silicide region.

    Abstract translation: 一种用于制造集成电路的方法包括在半导体衬底上形成临时栅极结构。 临时栅极结构包括设置在两个间隔结构之间的临时栅极材料。 该方法还包括形成覆盖临时栅极结构和半导体衬底的第一定向硅氮化物衬垫，蚀刻覆盖临时栅极结构的第一定向氮化硅衬底和临时栅极材料，以在间隔物结构之间形成沟槽，同时留下 定向氮化硅衬垫覆盖半导体衬底就位，并在沟槽中形成置换金属栅极结构。 集成电路包括覆盖半导体衬底的替代金属栅极结构，覆盖半导体衬底并邻近置换栅结构定位的硅化物区; 覆盖所述替代栅极结构的一部分的定向氮化硅衬垫; 以及与硅化物区域电连通的接触插塞。

    DOUBLE PATTERNING METHOD
    20.
    发明申请
    DOUBLE PATTERNING METHOD 有权
    双重图案方法

    公开(公告)号：US20140024215A1

    公开(公告)日：2014-01-23

    申请号：US13555306

    申请日：2012-07-23

    Applicant: Kangguo Cheng ,  Bruce B. Doris ,  Ali Khakifirooz ,  Ying Zhang

    Inventor： Kangguo Cheng ,  Bruce B. Doris ,  Ali Khakifirooz ,  Ying Zhang

    IPC: B44C1/22 ,  H01B13/00 ,  H01L21/308

    CPC classification number: H01L21/3086 ,  H01B13/00 ,  H01B19/04 ,  H01L21/0337 ,  H01L21/3081 ,  H01L21/32134 ,  H01L21/32137

    Abstract: Disclosed is an improved double patterning method for forming openings (e.g., vias or trenches) or mesas on a substrate. This method avoids the wafer topography effects seen in prior art double patterning techniques by ensuring that the substrate itself is only subjected to a single etch process. Specifically, in the method, a first mask layer is formed on the substrate and processed such that it has a doped region and multiple undoped regions within the doped region. Then, either the undoped regions or the doped region can be selectively removed in order to form a mask pattern above the substrate. Once the mask pattern is formed, an etch process can be performed to transfer the mask pattern into the substrate. Depending upon whether the undoped regions are removed or the doped region is removed, the mask pattern will form openings (e.g., vias or trenches) or mesas, respectively, on the substrate.

    Abstract translation: 公开了一种用于在基板上形成开口（例如，通孔或沟槽）或台面的改进的双重图案化方法。 该方法通过确保衬底本身仅经历单次蚀刻工艺来避免现有技术的双重图案化技术中所见到的晶片形貌效应。 具体地说，在该方法中，在衬底上形成第一掩模层并进行处理，使得其在掺杂区域内具有掺杂区域和多个未掺杂区域。 然后，可以选择性地去除未掺杂区域或掺杂区域，以在衬底上方形成掩模图案。 一旦形成掩模图案，就可以执行蚀刻工艺以将掩模图案转印到基板中。 取决于未掺杂的区域是去除还是去除掺杂区域，掩模图案将分别在衬底上形成开口（例如，通孔或沟槽）或台面。

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