公开(公告)号：US06320819B2

公开(公告)日：2001-11-20

申请号：US09733961

申请日：2000-12-12

申请人： Hiroyoshi Tomita ,  Tatsuya Kanda

发明人： Hiroyoshi Tomita ,  Tatsuya Kanda

IPC分类号： G11C800

CPC分类号： G11C7/1066 ,  G11C7/1072 ,  G11C8/00 ,  G11C8/04 ,  G11C8/18

摘要： A semiconductor device which receives addresses in synchronism with a clock signal and receives data in synchronism with a strobe signal includes address-latch circuits, a first control circuit which selects one of the address-latch circuits in sequence in response to the clock signal, and controls the selected one of the address-latch circuits to latch a corresponding one of the addresses in response to the clock signal, and a second control circuit which selects one of the address-latch circuits in sequence in response to the strobe signal, and controls the selected one of the address-latch circuits to output a corresponding one of the addresses in response to the strobe signal.

公开(公告)号：US06318707B1

公开(公告)日：2001-11-20

申请号：US09536467

申请日：2000-03-28

申请人： Kota Hara ,  Hiroyoshi Tomita ,  Naoharu Shinozaki

发明人： Kota Hara ,  Hiroyoshi Tomita ,  Naoharu Shinozaki

IPC分类号： G11C800

CPC分类号： G11C7/1084 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/1069 ,  G11C7/109 ,  G11C7/22 ,  G11C7/225

摘要： A semiconductor integrated circuit device includes a clock buffer circuit receiving a clock signal, a data buffer circuit receiving a data signal, an output circuit outputting the data signal from the data buffer circuit in accordance with the clock signal from the clock buffer circuit, and an adjustment circuit adjusting timings of the clock signal and the data signals.

摘要翻译： 一种半导体集成电路装置，包括接收时钟信号的时钟缓冲电路，接收数据信号的数据缓冲电路，根据来自时钟缓冲器电路的时钟信号从数据缓冲电路输出数据信号的输出电路，以及 调整电路调整时钟信号和数据信号的定时。

公开(公告)号：US06295245B1

公开(公告)日：2001-09-25

申请号：US09385004

申请日：1999-08-27

申请人： Hiroyoshi Tomita ,  Tatsuya Kanda

发明人： Hiroyoshi Tomita ,  Tatsuya Kanda

IPC分类号： G11C1300

CPC分类号： G11C7/109 ,  G11C7/1066 ,  G11C7/1072 ,  G11C7/1078 ,  G11C7/1087 ,  G11C7/1093 ,  G11C7/222 ,  G11C11/4096

摘要： A write data input circuit for a double data rate (DDR) SDRAM acquires write data at both a rising and falling edge of a clock signal. The input circuit includes a command input buffer for receiving external commands, such as a read, write or refresh command. An external command latch circuit connected to the input buffer latches the external command in sync with a first clock signal. A decoder decodes the latched external command. A write determination circuit also receives the (undecoded) external command and generates an enable signal if the external command is a write command. A data input buffer is activated by the enable signal and receives write data. A data latch circuit latches the write data provided to the data input buffer in sync with a second clock signal.

摘要翻译： 双数据速率（DDR）SDRAM的写数据输入电路在时钟信号的上升沿和下降沿都获取写数据。 输入电路包括用于接收诸如读取，写入或刷新命令的外部命令的命令输入缓冲器。 连接到输入缓冲器的外部命令锁存电路与第一时钟信号同步地锁存外部指令。 解码器解码锁定的外部命令。 如果外部命令是写命令，则写入确定电路还接收（未解码）外部命令并产生使能信号。 数据输入缓冲器由使能信号激活并接收写入数据。 数据锁存电路与第二时钟信号同步地锁存提供给数据输入缓冲器的写入数据。

公开(公告)号：US06242954B1

公开(公告)日：2001-06-05

申请号：US09385010

申请日：1999-08-27

申请人： Nobutaka Taniguchi ,  Hiroyoshi Tomita

发明人： Nobutaka Taniguchi ,  Hiroyoshi Tomita

IPC分类号： H04L708

CPC分类号： H03L7/0814 ,  G06F1/10 ,  H03L7/0818 ,  H03L7/087

摘要： The present invention has a hierarchical DLL circuit comprising a rough DLL circuit for phase adjustment by rough delay unit and a fine DLL circuit for phase adjustment by smaller, fine delay unit. When phase adjustment begins, only the rough DLL circuit operates; when the rough DLL circuit locks on, phase adjustment by the rough DLL circuit ends and the delay amount of the rough DLL circuit is set. When the rough DLL circuit locks on, the fine DLL circuit is caused to operate. In this way, the phase of the timing clock generated by the DLL circuit is adjusted only by fine delay units even if the phase of the reference clock is temporarily shifted by a large amount due to power source noise or the like. Consequently, in the event of temporary phase shifting, the amount of jitter in the timing clock can be suppressed to the small amount of a fine delay unit. Phase adjustment by the rough DLL circuit is stopped by ending phase comparison by the phase comparison circuit, or ending the input of the clock to the phase comparison circuit, for example.

摘要翻译： 本发明具有分级DLL电路，其包括用于通过粗略延迟单元进行相位调整的粗略DLL电路和用于通过较小的精细延迟单元进行相位调整的精细DLL电路。 当相位调整开始时，只有粗略的DLL电路运行; 当粗体DLL电路锁定时，粗体DLL电路的相位调整结束，并设置粗略电路的延迟量。 当粗体DLL电路锁定时，使细小的DLL电路工作。 以这种方式，即使由于电源噪声等而使参考时钟的相位暂时移位了大量，由DLL电路产生的定时时钟的相位仅被微调延迟单元调整。 因此，在临时相移的情况下，可以将定时时钟中的抖动量抑制到微小的延迟单元的量。 例如，通过由相位比较电路结束相位比较或将时钟的输入结束到相位比较电路来停止粗略DLL电路的相位调整。

公开(公告)号：US6075393A

公开(公告)日：2000-06-13

申请号：US998478

申请日：1997-12-29

申请人： Hiroyoshi Tomita ,  Yoshihiro Takemae

发明人： Hiroyoshi Tomita ,  Yoshihiro Takemae

IPC分类号： G11C11/413 ,  G06F1/10 ,  G06F12/00 ,  G11C7/00 ,  G11C7/10 ,  G11C7/22 ,  G11C11/401 ,  G11C11/407 ,  H03K5/135 ,  H03L7/081 ,  H03L7/00

CPC分类号： G11C7/222 ,  G11C7/1078 ,  G11C7/22 ,  H03L7/0812

摘要： A clock synchronous semiconductor device system and semiconductor devices used with the system have the read and write operations performed at a proper timing without increasing the types of clock or the amount of wiring. The system includes a plurality of semiconductor devices operated in synchronism with a clock. One of the semiconductor devices operates as a controller for producing a signal related to the controlling of the remaining semiconductor devices. A clock signal line for transmitting a clock to each semiconductor device is arranged in parallel with the other signal lines. A clock source is arranged at a position far from the controller not to cause any skew when the read data arrive at the controller from the remaining semiconductor devices. The timing at which each memory retrieves the write data from the controller is adjusted by an input timing adjusting circuit included in each memory, thereby permitting each memory to retrieve the write data at an optimum timing.

摘要翻译： 与系统一起使用的时钟同步半导体器件系统和半导体器件具有在适当的定时执行的读和写操作，而不增加时钟的类型或布线的数量。 该系统包括与时钟同步操作的多个半导体器件。 其中一个半导体器件用作用于产生与其余半导体器件的控制有关的信号的控制器。 用于将时钟发送到每个半导体器件的时钟信号线与其他信号线并联布置。 当远离控制器的位置处的时钟源被布置在读取数据从其余半导体器件到达控制器时不会产生任何偏斜。 通过每个存储器中包括的输入定时调整电路调整每个存储器从控制器检索写数据的定时，从而允许每个存储器在最佳定时检索写数据。

公开(公告)号：US6066969A

公开(公告)日：2000-05-23

申请号：US130168

申请日：1998-08-06

申请人： Kenichi Kawasaki ,  Yasuharu Sato ,  Hiroyoshi Tomita

发明人： Kenichi Kawasaki ,  Yasuharu Sato ,  Hiroyoshi Tomita

IPC分类号： G06F1/10 ,  G11C11/407 ,  G11C11/4076 ,  H01L27/00 ,  H03K5/13 ,  H03L7/00 ,  H03L7/081 ,  H03L7/06

CPC分类号： H03L7/0805 ,  H03L7/0814

摘要： A semiconductor device includes a variable-delay circuit which delays an input-clock signal to generate a delay clock signal, a clock-control circuit which selects one of the input-clock signal and the delayed clock signal, an output circuit which outputs data in synchronism with a clock signal selected by the clock-control circuit, and a DLL circuit which adjusts a delay of the variable-delay circuit. The DLL circuit includes a delay-control circuit which adjusts the delay of the variable-delay circuit, and a clock-selection circuit which controls the clock-control circuit to select one of the input-clock signal and the delayed clock signal. The variable-delay circuit is controlled such that the delay is not increased when the input-clock signal is selected by the clock-selection circuit.

摘要翻译： 一种半导体器件包括延迟输入时钟信号以产生延迟时钟信号的可变延迟电路，选择输入时钟信号和延迟时钟信号之一的时钟控制电路，输出电路，输出数据 与由时钟控制电路选择的时钟信号的同步，以及调整可变延迟电路的延迟的DLL电路。 DLL电路包括调整可变延迟电路的延迟的延迟控制电路和控制时钟控制电路以选择输入时钟信号和延迟的时钟信号之一的时钟选择电路。 控制可变延迟电路，使得当时钟选择电路选择输入时钟信号时，延迟不增加。

公开(公告)号：US5912858A

公开(公告)日：1999-06-15

申请号：US1649

申请日：1997-12-31

申请人： Hiroyoshi Tomita ,  Yuji Kurita

发明人： Hiroyoshi Tomita ,  Yuji Kurita

IPC分类号： G11C11/413 ,  G06F1/12 ,  G06F13/42 ,  G11C7/10 ,  G11C7/22 ,  G11C11/407 ,  G11C11/409 ,  H04L7/00 ,  G11C8/00 ,  G11C7/00

CPC分类号： G11C7/1093 ,  G11C7/1072 ,  G11C7/1078 ,  G11C7/22

摘要： A semiconductor memory device, to which a plurality of command signals are supplied in synchronous with a clock, comprises a plurality of input circuits, having a sampling unit for inputting said command signals and said clock and sampling said command signals in synchronous with said clock, and an output unit for outputting said sampled command signals; a command decoder for receiving the command signals output by said plurality of input circuits, decoding said plurality of command signals and generating a corresponding control signal; a memory element, which implements a variety of operational modes in response to said control signals; an output timing signal generator circuit, having a circuit architecture equivalent to at least the sampling unit of said input circuit, for sampling a predetermined signal level in synchronous with said clock, and for generating an output timing signal based on the timing of the operational delay time of said sampling unit; and wherein said input circuit outputs said sampled command signals in response to said output timing signal.

摘要翻译： 与时钟同步地供给多个命令信号的半导体存储器件包括多个输入电路，具有用于输入所述命令信号和所述时钟的采样单元，并与所述时钟同步地对所述命令信号进行采样， 以及输出单元，用于输出所述采样的指令信号; 命令解码器，用于接收由所述多个输入电路输出的命令信号，解码所述多个命令信号并产生相应的控制信号; 存储元件，其响应于所述控制信号实现各种操作模式; 输出定时信号发生器电路，具有与至少所述输入电路的采样单元相当的电路结构，用于与所述时钟同步地采样预定信号电平，并且用于基于所述操作延迟的定时产生输出定时信号 所述采样单元的时间; 并且其中所述输入电路响应于所述输出定时信号而输出所述采样的指令信号。

公开(公告)号：US5896347A

公开(公告)日：1999-04-20

申请号：US925458

申请日：1997-09-08

申请人： Hiroyoshi Tomita ,  Yoshihiro Takemae

发明人： Hiroyoshi Tomita ,  Yoshihiro Takemae

IPC分类号： G11C11/413 ,  G11C7/10 ,  G11C7/22 ,  G11C11/401 ,  G11C11/407 ,  G11C11/409 ,  H03L7/00 ,  G11C8/00

CPC分类号： G11C7/1093 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/1066 ,  G11C7/1072 ,  G11C7/1078 ,  G11C7/22 ,  G11C7/222

摘要： A semiconductor memory system using a synchronous memory and operating at a higher speed due to a reduced margin required when reading data from the SDRAM, and a semiconductor memory device for achieving the same are disclosed. The semiconductor memory system comprises at least one semiconductor memory device and a control device for performing data input/output to and from the semiconductor memory device, wherein the control device outputs data to be stored in the semiconductor memory device, synchronously with a first synchronizing signal that the control device outputs, and the semiconductor memory device delivers output data therefrom synchronously with a second synchronizing signal that the semiconductor memory device outputs. In the thus constructed semiconductor memory system, the semiconductor memory device incorporates an output phase shift circuit which introduces a prescribed phase angle between the output data and second synchronizing signal, and provisions are made so that at the semiconductor memory device side the output data and the second synchronizing signal are controlled precisely at the prescribed phase angle with respect to each other, and so that a latch pulse can be immediately generated at the controller side upon reception of a data strobe signal.

摘要翻译： 公开了一种使用同步存储器并且由于在从SDRAM读取数据时所需的余量减小而以更高速度工作的半导体存储器系统，以及用于实现其的半导体存储器件。 半导体存储器系统包括至少一个半导体存储器件和用于对半导体存储器件进行数据输入/输出的控制器件，其中控制器件与第一同步信号同步地输出要存储在半导体存储器件中的数据 控制装置输出，半导体存储装置与半导体存储装置输出的第二同步信号同步地输出输出数据。 在这样构成的半导体存储器系统中，半导体存储器件包括在输出数据和第二同步信号之间引入规定相位角的输出移相电路，并且在半导体存储器件侧进行输出数据和 第二同步信号相对于彼此精确地以规定的相位角被控制，并且使得在接收数据选通信号时可以在控制器侧立即产生锁存脉冲。

公开(公告)号：US5881009A

公开(公告)日：1999-03-09

申请号：US1655

申请日：1997-12-31

申请人： Hiroyoshi Tomita

发明人： Hiroyoshi Tomita

IPC分类号： G11C11/408 ,  G11C7/10 ,  G11C11/401 ,  G11C11/407 ,  G11C7/00

CPC分类号： G11C7/1018 ,  G11C7/1042

摘要： In the present invention data from the odd memory cell array is latched to a data-hold circuit at a fast timing, which ignores the delay time of the +1 arithmetic circuit, and outputs that data to the output terminal. Further, when the supplied column address is even, data from the even memory cell array is latched to a data-hold circuit at a fast timing similar to that described above, and when the column address is odd, this data is latched to a data-hold circuit with a delay equivalent to the delay of the +1 arithmetic circuit. In this case, since the output of even output data to an output terminal occurs following the output of odd output data, the overall output operation is not affected comparing to the conventional one. Another aspect of the present invention provides a circuit, which shifts one bit combinations of the second and third bits following the least significant bit in a column address. And when the column address is even, the second and third bits address as-is are supplied into an even decoder, and when the column address is odd, supplies a shifted combination of the second and third bits address are supplied to the even decoder. Since this shift operation does not require the same delay time as conventional arithmetic operations, both even and odd CAS delay times can be reduced.

摘要翻译： 在本发明中，来自奇数存储单元阵列的数据以快速定时锁存到数据保持电路，忽略+1运算电路的延迟时间，并将该数据输出到输出端。 此外，当所提供的列地址为偶数时，来自偶数存储单元阵列的数据以类似于上述的快速定时被锁存到数据保持电路，并且当列地址为奇数时，该数据被锁存到数据 -hold电路的延迟等于+1运算电路的延迟。 在这种情况下，由于在输出奇数输出数据之后输出偶数输出数据到输出端子，所以与常规输出操作相比，整体输出操作不受影响。 本发明的另一方面提供一种电路，其将列地址中的最低有效位之后的第二和第三位的一位组合移位。 而当列地址为偶数时，第二位和第三位地址被提供给偶译码器，当列地址为奇数时，提供第二位和第三位地址的移位组合提供给偶译码器。 由于该移位操作不需要与常规算术运算相同的延迟时间，所以可以减少偶数和奇数CAS延迟时间。

公开(公告)号：US5384789A

公开(公告)日：1995-01-24

申请号：US12644

申请日：1993-02-03

申请人： Hiroyoshi Tomita

发明人： Hiroyoshi Tomita

IPC分类号： G11C11/401 ,  G06F11/10 ,  G11C29/00 ,  G11C29/42 ,  H01L27/10

CPC分类号： G06F11/1008 ,  G06F11/1076

摘要： A semiconductor memory device has a cell and amplifier portion, a syndrome generation circuit, an error checking and correction circuit, and a plurality of memory control blocks. The cell and amplifier portion has a memory cell array, a sense amplifier array, and a column gate array, and each of the memory control blocks has a data bus amplifier, a write amplifier, and a syndrome decoder circuit which decodes syndrome output from the syndrome generation circuit. Consequently, an occupancy area can be reduced by decreasing the number of wiring lines, and a large scale integration and a low power consumption can be realized.

摘要翻译： 半导体存储器件具有单元和放大器部分，校正子产生电路，错误校验和校正电路以及多个存储器控制块。 单元和放大器部分具有存储单元阵列，读出放大器阵列和列门阵列，并且每个存储器控制块具有数据总线放大器，写入放大器和校正子解码器电路，其对来自 综合征发生电路。 因此，可以通过减少布线数量来减少占用面积，并且可以实现大规模集成和低功耗。