公开(公告)号：US06232813B1

公开(公告)日：2001-05-15

申请号：US09419837

申请日：1999-10-15

申请人： Sang-bo Lee

发明人： Sang-bo Lee

IPC分类号： H04L708

CPC分类号： H03L7/0814 ,  H03K5/133

摘要： Phase locked loop integrated circuits include a phase detection circuit, a variable delay device and a delay control circuit. The variable delay device and delay control circuit provide improved characteristics by increasing the signal frequency bandwidth of the delay locked loop integrated circuit in a preferred manner. The phase detection circuit is configured to perform the functions of comparing first and second periodic signals and generating a phase control signal (e.g., VCON1) having a first property (e.g., magnitude) that is proportional to a difference in phase between the first and second periodic signals. The delay control circuit is responsive to the phase control signal VCON1 and generates a delay control signal that is provided to the variable delay device. The delay control circuit may comprise a counter, a first comparator, a second comparator and a shift register. The variable delay device includes a variable delay line and a compensation delay device. The variable delay line may contain a string of unit delay devices and a string of switches that each have an input electrically coupled to an output of a corresponding unit delay device. Each of the unit delay devices in the string may provide a fixed delay or a variable delay that is influenced (e.g., increased) by changes (e.g., increases) in the magnitude of the phase control signal VCON1.

摘要翻译： 锁相环集成电路包括相位检测电路，可变延迟器件和延迟控制电路。 可变延迟装置和延迟控制电路通过以优选的方式增加延迟锁定环集成电路的信号频率带宽来提供改进的特性。 相位检测电路被配置为执行比较第一和第二周期信号的功能，并产生具有与第一和第二周期信号之间的相位差成比例的第一属性（例如，幅度）的相位控制信号（例如，VCON1） 周期信号。 延迟控制电路响应于相位控制信号VCON1，并产生提供给可变延迟装置的延迟控制信号。 延迟控制电路可以包括计数器，第一比较器，第二比较器和移位寄存器。 可变延迟装置包括可变延迟线和补偿延迟装置。 可变延迟线可以包含一串单位延迟装置和一串开关，每个开关具有电耦合到相应的单位延迟装置的输出的输入。 串中的每个单元延迟装置可以通过相位控制信号VCON1的幅度的改变（例如，增加）来提供固定延迟或可变延迟。

公开(公告)号：US06829253B1

公开(公告)日：2004-12-07

申请号：US09723634

申请日：2000-11-28

申请人： Havish Koorapaty ,  Robert A. Zak ,  Carl B. Toot

发明人： Havish Koorapaty ,  Robert A. Zak ,  Carl B. Toot

IPC分类号： H04L708

CPC分类号： H04W56/0085 ,  H04B7/2684 ,  H04L7/042 ,  H04L7/08

摘要： Methods and systems for a transceiver to acquire synchronization to a channel in a TDMA communications system by identifying a known synchronization word in a burst received at the transceiver over the channel are provided. Pursuant to these methods and systems a first uncertainty window and a second uncertainty window are defined within a burst that is received over the channel. The transceiver may search in these uncertainty windows for the known synchronization word, where the first uncertainty window is smaller than the second uncertainty window. The first uncertainty window is first searched for the known synchronization word. It may then be determined if the known synchronization word has been located within the first uncertainty window. If it has not been, the second uncertainty window is then searched for the known synchronization word.

摘要翻译： 提供了一种用于通过识别通过信道在收发器处接收的突发中的已知同步字来获取TDMA通信系统中的信道的同步的方法和系统。 根据这些方法和系统，在通过信道接收的脉冲串内定义第一不确定性窗口和第二不确定性窗口。 收发器可以在这些不确定性窗口中搜索已知的同步字，其中第一不确定性窗口小于第二不确定性窗口。 第一个不确定窗口首先搜索已知的同步字。 然后可以确定已知的同步字是否已经位于第一不确定性窗口内。 如果没有，则搜索第二不确定性窗口以获得已知的同步字。

公开(公告)号：US06763079B1

公开(公告)日：2004-07-13

申请号：US09252910

申请日：1999-02-19

申请人： Hisashi Iwamoto

发明人： Hisashi Iwamoto

IPC分类号： H04L708

CPC分类号： G11C29/12015 ,  G01R31/31725 ,  G01R31/31727 ,  G11C29/02 ,  G11C29/50012 ,  H03K5/133 ,  H03K2005/00071 ,  H03K2005/00241 ,  H03L7/0814 ,  H03L7/089

摘要： A shift register which outputs a delay control signal for a delay line is made controllable at a test mode by a TEST MODE address buffer receiving an external address as a control signal and a phase comparator. Thus whether the delay of the delay line is correctly controlled or not can be confirmed through observation of an internal clock signal int. CLK output from an output buffer at the test and an external clock signal ext. CLK.

摘要翻译： 输出用于延迟线的延迟控制信号的移位寄存器通过接收作为控制信号的外部地址的TEST MODE地址缓冲器和相位比较器在测试模式下被控制。 因此，可以通过观察内部时钟信号int来确认延迟线的延迟是否被正确控制。 来自测试时的输出缓冲器的CLK输出和外部时钟信号分频。 CLK。

公开(公告)号：US06452432B2

公开(公告)日：2002-09-17

申请号：US09816968

申请日：2001-03-23

申请人： Kyu-hyoun Kim

发明人： Kyu-hyoun Kim

IPC分类号： H04L708

CPC分类号： G11C7/222 ,  G11C7/1072 ,  H03K5/1565 ,  H03L7/07 ,  H03L7/0814 ,  H03L7/087

摘要： A signal processing circuit includes a first delay locked loop (DLL) circuit that generates a first intermediate output signal in response to an input signal and a phase difference between a leading edge of a reference signal and a leading edge of a feedback signal and a second DLL circuit that generates a second intermediate output signal in response to the input signal and a phase difference between a trailing edge of the reference signal and a trailing edge of the feedback signal. Because the first and second intermediate output signals are based on the phase difference between the reference signal and the leading and trailing edges of a feedback signal, respectively, and the first and second intermediate output signals are not derived from the reference signal, the jitter that may be introduced into the first and second intermediate output signals may be reduced.

摘要翻译： 信号处理电路包括响应于输入信号产生第一中间输出信号的第一延迟锁定环（DLL）电路和参考信号的前沿与反馈信号的前沿之间的相位差，第二延迟锁定环 DLL电路，其响应于输入信号产生第二中间输出信号，以及基准信号的后沿与反馈信号的后沿之间的相位差。 因为第一和第二中间输出信号分别基于参考信号与反馈信号的前沿和后沿之间的相位差，并且第一和第二中间输出信号不是从参考信号导出的，所以抖动 可以引入第一和第二中间输出信号。

公开(公告)号：US06738392B1

公开(公告)日：2004-05-18

申请号：US09671965

申请日：2000-09-27

申请人： Andrew J. Thurston

发明人： Andrew J. Thurston

IPC分类号： H04L708

CPC分类号： H04J3/1611 ,  H04J3/0608

摘要： A method for high-speed signal framing of an incoming bit stream includes receiving the incoming bit stream in a datapath and locating a predetermined framing pattern in the datapath by finding a predetermined number of repetitions of a first portion of the framing pattern, bit aligning the bits in the datapath based on the predetermined number of repetitions of the first portion, priority encoding bits in a next cycle of the datapath, identifying a location of a second portion of the framing pattern, word aligning the priority encoded bits. The method includes declaring the bit stream as in frame. The incoming bit stream is over a datapath of at least 64 bits and the predetermined number of repetitions is at least three repetitions. Further, the incoming bitstream is a parallelized bitstream, the parallelization being performed in a shift register. An apparatus disposed in a communication system includes a shift register to receive an incoming bitstream that is configured to parallelize the incoming bitstream, a bit-aligning multiplexer coupled to the shift register that bit-aligns the parallelized bitstream according to a first portion of a framing pattern, a priority encoder coupled to the bit-aligning multiplexer that locates a priority byte in the parallelized bitstream identified in a second portion of the framing pattern and identifies a transition between the first portion and the second portion of the framing pattern, a byte-aligning multiplexer coupled to the priority encoder that byte-aligns the parallelized bitstream according to the priority byte and determining frame borders of the incoming bitstream.

摘要翻译： 一种用于进入比特流的高速信号成帧的方法包括：在数据通路中接收输入比特流，并通过找到成帧模式的第一部分的预定数量的重复来定位数据路径中的预定成帧模式， 基于第一部分的预定重复次数的数据路径中的比特，数据路径的下一个周期中的优先级编码比特，识别成帧模式的第二部分的位置，对准优先编码比特的字。 该方法包括在帧中声明比特流。 输入比特流在至少64位的数据通路之上，并且预定次数的重复是至少三次重复。 此外，输入比特流是并行比特流，并行化在移位寄存器中执行。 设置在通信系统中的装置包括：移位寄存器，用于接收被配置为并行化输入比特流的输入比特流;耦合到移位寄存器的比特对齐多路复用器，其根据成帧的第一部分对齐并行比特流 耦合到位对准多路复用器的优先级编码器，其定位在成帧模式的第二部分中识别的并行化比特流中的优先级字节，并识别成帧模式的第一部分和第二部分之间的转换， 耦合到优先级编码器的对准多路复用器，其根据优先级字节对并行比特流进行字节对齐，并确定输入比特流的帧边界。

公开(公告)号：US06636533B1

公开(公告)日：2003-10-21

申请号：US09556734

申请日：2000-04-21

申请人： Yurij Baransky ,  Hubertus Franke ,  Pratap Pattnaik

发明人： Yurij Baransky ,  Hubertus Franke ,  Pratap Pattnaik

IPC分类号： H04L708

CPC分类号： H04N21/8541 ,  H04N7/163 ,  H04N21/235 ,  H04N21/2365 ,  H04N21/26216 ,  H04N21/4331 ,  H04N21/4347 ,  H04N21/435 ,  H04N21/84 ,  H04N21/8547

摘要： The present invention is a process in which broadcasters can supplement existing multimedia streams such as video and audio with additional multimedia streams in a coordinated and integrated way, allowing users, after reception of the broadcast stream, to select which substream to use, without requiring an upstream channel to communicate this user preference back to the server or any additional bandwidth to broadcast these additional streams.

摘要翻译： 本发明是广播机构可以以协调和集成的方式补充现有多媒体流如视频和音频的附加多媒体流，允许用户在接收广播流之后选择要使用的子流，而不需要 上行信道将该用户偏好传送回服务器或任何附加带宽以广播这些附加流。

公开(公告)号：US06359908B1

公开(公告)日：2002-03-19

申请号：US09136380

申请日：1998-08-19

申请人： Masaaki Soda

发明人： Masaaki Soda

IPC分类号： H04L708

CPC分类号： H04J3/0608 ,  H04J2203/0089

摘要： A frame synchronous circuit enables a frame synchronization in relation to high speed SDH (Synchronous Digital Hierarchy) signal to be realized with simple constitution. A shift register which performs serial-parallel conversion of an STM-N (Synchronous Transport Module-N (=1, 2, 3, . . . )) signal by 1-byte unit, is in use by way of shift registers 4, and 7 with parallel configuration inputting data alternately in every 1-bit, thus enabling sufficient time for processing operation of the data to be secured. Appearance of A1-byte on two shift registers can be generated by way of two kinds of patterns of output positions which are shifted by one bit with each other caused by input order toward the shift register. Thereby, when the A1-byte detecting circuit 6 detects the A1-byte at an inappropriate output position, slowing the STM-N signal by 1 bit at the 1-bit delay circuit in order to reverse the input order such that the A1-byte is detected at the normal output position. Subsequently, the counter 3 with 1-byte cycle which causes the latched-circuits 5, and 8 to operate is reset so as to output parallel data with 1-byte unit by adjusting to the detecting timing (phase).

摘要翻译： 帧同步电路能够以简单的结构实现与高速SDH（同步数字体系）信号相关的帧同步。 以1字节为单位进行STM-N（同步传输模块-N（= 1,2,3等））信号的串行 - 并行转换的移位寄存器通过移位寄存器4， 和7，并行配置在每1位交替地输入数据，从而使得足够的时间来处理数据的操作。 两个移位寄存器上的A1字节的外观可以通过输出位置的两种模式生成，这两种模式由输入顺序向移位寄存器相互移位一个位。 因此，当A1字节检测电路6在不适当的输出位置检测到A1字节时，在1位延迟电路中将STM-N信号减1位，以便反转输入顺序，使得A1字节 在正常输出位置检测。 随后，使锁存电路5和8工作的具有1字节周期的计数器3被复位，以便通过调整到检测定时（相位）来输出具有1字节单位的并行数据。

公开(公告)号：US06246736B1

公开(公告)日：2001-06-12

申请号：US09207250

申请日：1998-12-09

申请人： Alan Charles Coady

发明人： Alan Charles Coady

IPC分类号： H04L708

CPC分类号： H04J3/0608

摘要： A method and apparatus for detecting framing alignment sequence within a received bit stream. A stream state memory is assigned for each possible location of the framing alignment sequence. Bits of a particular stream are loaded into the respective stream state memory. If the bits do not match an acceptable subsequence of the framing alignment sequence then the stream is eliminated from consideration by writing an exile state to the respective stream state memory. Then subsequently received bits are used to transition either to the next state if the next bit is a correct bit in the framing alignment sequence, or to the exile state if the bit is not the correct bit. After all of the streams have been exiled but one, the remaining stream may contain the framing alignment sequence. However, it may be that a certain number of correctly received bits are required to declare in-frame with sufficient certainty in which case incoming bits will continue to be processed until this is satisfied. Examples are given relating to DS1 superframe and extended superframe framing alignment sequences.

摘要翻译： 一种用于检测接收到的比特流内的成帧对准序列的方法和装置。 为成帧对准序列的每个可能位置分配流状态存储器。 特定流的比特加载到相应的流状态存储器中。 如果比特与成帧比对序列的可接受子序列不匹配，则通过将流放状态写入相应的流状态存储器来消除考虑流。 然后，如果下一位是成帧比对序列中的正确位，则后续接收到的位用于转换到下一个状态，如果该位不是正确的位，则转换到流放状态。 在所有流已经流放但一个流之后，剩余的流可以包含成帧对准序列。 然而，可能需要一定数量的正确接收的比特以足够的确定性在帧内声明，在这种情况下，输入比特将继续被处理，直到满足为止。 给出了与DS1超帧和扩展超帧成帧对准序列有关的示例。

公开(公告)号：US06242954B1

公开(公告)日：2001-06-05

申请号：US09385010

申请日：1999-08-27

申请人： Nobutaka Taniguchi ,  Hiroyoshi Tomita

发明人： Nobutaka Taniguchi ,  Hiroyoshi Tomita

IPC分类号： H04L708

CPC分类号： H03L7/0814 ,  G06F1/10 ,  H03L7/0818 ,  H03L7/087

摘要： The present invention has a hierarchical DLL circuit comprising a rough DLL circuit for phase adjustment by rough delay unit and a fine DLL circuit for phase adjustment by smaller, fine delay unit. When phase adjustment begins, only the rough DLL circuit operates; when the rough DLL circuit locks on, phase adjustment by the rough DLL circuit ends and the delay amount of the rough DLL circuit is set. When the rough DLL circuit locks on, the fine DLL circuit is caused to operate. In this way, the phase of the timing clock generated by the DLL circuit is adjusted only by fine delay units even if the phase of the reference clock is temporarily shifted by a large amount due to power source noise or the like. Consequently, in the event of temporary phase shifting, the amount of jitter in the timing clock can be suppressed to the small amount of a fine delay unit. Phase adjustment by the rough DLL circuit is stopped by ending phase comparison by the phase comparison circuit, or ending the input of the clock to the phase comparison circuit, for example.

摘要翻译： 本发明具有分级DLL电路，其包括用于通过粗略延迟单元进行相位调整的粗略DLL电路和用于通过较小的精细延迟单元进行相位调整的精细DLL电路。 当相位调整开始时，只有粗略的DLL电路运行; 当粗体DLL电路锁定时，粗体DLL电路的相位调整结束，并设置粗略电路的延迟量。 当粗体DLL电路锁定时，使细小的DLL电路工作。 以这种方式，即使由于电源噪声等而使参考时钟的相位暂时移位了大量，由DLL电路产生的定时时钟的相位仅被微调延迟单元调整。 因此，在临时相移的情况下，可以将定时时钟中的抖动量抑制到微小的延迟单元的量。 例如，通过由相位比较电路结束相位比较或将时钟的输入结束到相位比较电路来停止粗略DLL电路的相位调整。