公开(公告)号：US06801548B1

公开(公告)日：2004-10-05

申请号：US09608461

申请日：2000-06-30

申请人： Douglas E. Duschatko ,  Lane B. Quibodeaux ,  Robert A. Hall ,  Andrew J. Thurston

发明人： Douglas E. Duschatko ,  Lane B. Quibodeaux ,  Robert A. Hall ,  Andrew J. Thurston

IPC分类号： H04L1228

CPC分类号： H04J3/1611

摘要： An apparatus and method for a synchronous optical network (SONET) includes ordering a plurality of signals of a first type in one or more line cards for transmit to one or more types of line cards, wherein the ordering of the first type of signals creates a plurality of independent signals of a second type, and transmitting the plurality of the first type of signals to the one or more types of line cards, wherein the independence of the signals of the second type permits the one or more types of signals of the second type to be in an arbitrary order. The method and apparatus includes ordering in a plurality of modules to assign to a variable A a number of basic modules on the one or more line cards, assign to a variable B a number of processors adapted for STS-N signals on the one or more line cards, calculate a variable C by dividing A by B, C being the number of basic module channels common to each of the processors, calculate a variable D by dividing C by three, D being a number of contiguous channels, divide each STS-N signal into N/D portions, each portion including up to D bytes, and for each portion of the STS-N signal, select one of the number of processors adapted for STS-N signals, and transmit the portion of the STS-N signal to the one of the number of processors.

摘要翻译： 一种用于同步光网络（SONET）的装置和方法包括在一个或多个线卡中排序第一类型的多个信号以发送到一种或多种类型的线卡，其中第一类型的信号的排序创建一个 多个第二类型的独立信号，并且将多个第一类型的信号发送到一种或多种类型的线路卡，其中第二类型的信号的独立性允许第二类型的信号的一种或多种类型的信号 类型为任意顺序。 该方法和装置包括在多个模块中订购以将一个或多个线路卡上的多个基本模块分配给变量A，向变量B分配适于在一个或多个线卡上的STS-N信号的多个处理器 通过将A除以B计算变量C，C是每个处理器共同的基本模块通道的数量，通过将C除以3来计算变量D，D是连续通道的数量，将每个STS- N信号转换成N / D部分，每个部分包括D字节，并且对于STS-N信号的每个部分，选择适合于STS-N信号的处理器数目之一，并发送STS-N的部分 信号到处理器数量之一。

公开(公告)号：US20080155382A1

公开(公告)日：2008-06-26

申请号：US12046049

申请日：2008-03-11

申请人： Qiujie Dong ,  Andrew J. Thurston

发明人： Qiujie Dong ,  Andrew J. Thurston

IPC分类号： H03M13/00 ,  G06F7/38 ,  G06F17/00 ,  G06F11/07

CPC分类号： H03M13/159 ,  H03M13/1515 ,  H03M13/158

摘要： Various methods and systems for implementing Reed Solomon multiplication sections from exclusive-OR (XOR) logic are disclosed. For example, a system includes a Reed Solomon multiplication section, which includes XOR-based logic. The XOR-based logic includes an input, an output, and one or more XOR gates. A symbol X is received at the input of the XOR-based logic. The one or more XOR gates are coupled to generate a product of a power of α and X at the output, wherein α is a root of a primitive polynomial of a Reed Solomon code. Such a Reed Solomon multiplication section, which can include one or more multipliers implemented using XOR-based logic, can be included in a Reed Solomon encoder or decoder.

摘要翻译： 公开了用于从异或（XOR）逻辑实现Reed Solomon乘法部分的各种方法和系统。 例如，系统包括Reed Solomon乘法部分，其包括基于XOR的逻辑。 基于XOR的逻辑包括输入，输出和一个或多个异或门。 在基于XOR的逻辑的输入处接收符号X. 一个或多个XOR门被耦合以在输出处产生α和X的幂的乘积，其中α是里德所罗门码的原始多项式的根。 这种Reed Solomon乘法部分可以包括在Reed Solomon编码器或解码器中，该部分可以包括使用基于XOR的逻辑实现的一个或多个乘法器。

公开(公告)号：US06983414B1

公开(公告)日：2006-01-03

申请号：US09821948

申请日：2001-03-30

申请人： Douglas E. Duschatko ,  Andrew J. Thurston

发明人： Douglas E. Duschatko ,  Andrew J. Thurston

IPC分类号： H03M13/00

CPC分类号： H04L1/0071 ,  H03M13/015 ,  H03M13/152 ,  H04L1/0045 ,  H04L1/0057

摘要： An OC-192 front-end application-specific integrated circuit (ASIC) de-interleaves an OC-192 signal to create four OC-48 signals, and decodes error-correction codes embedded in each of the four OC-48 signals. An error insertion circuit is also provided for verifying correct operation of encoding and decoding circuits. A desired number of errors may be programmed for insertion into the OC-48 data signals. Error insertion may be performed in an iterative fashion to insert into different data signals the desired number of errors, wherein the errors are placed within the code words of the data signals at different location permutations for each data signal. In one implementation, error verification is performed using an error accumulator located in the receiver, and means are provided for examining an error accumulator count of the error accumulator to see if the number of accumulated errors matches with the number of inserted errors.

摘要翻译： OC-192前端应用专用集成电路（ASIC）对OC-192信号进行解交织以产生四个OC-48信号，并解码嵌入在四个OC-48信号中的每一个中的纠错码。 还提供了用于验证编码和解码电路的正确操作的错误插入电路。 可以编程所需数量的错误以插入到OC-48数据信号中。 可以以迭代的方式执行错误插入，以将不同的数据信号插入到所需数量的错误中，其中在每个数据信号的不同位置排列中将错误置于数据信号的码字内。 在一个实现中，使用位于接收器中的错误累加器执行错误验证，并且提供用于检查错误累加器的错误累加器计数的装置，以查看累积错误的数量是否与插入的错误的数量匹配。

公开(公告)号：US06973041B1

公开(公告)日：2005-12-06

申请号：US09607912

申请日：2000-06-30

申请人： Douglas E. Duschatko ,  Lane B. Quibodeaux ,  Robert A. Hall ,  Andrew J. Thurston

发明人： Douglas E. Duschatko ,  Lane B. Quibodeaux ,  Robert A. Hall ,  Andrew J. Thurston

IPC分类号： H04J3/06 ,  H04J3/14 ,  H04L12/26 ,  H04L12/56

CPC分类号： H04L49/552 ,  H04J3/0623 ,  H04J3/14 ,  H04L49/101 ,  H04L49/351 ,  H04L49/40

摘要： In a data transmission network, such as SONET, a method and apparatus for the generation of a path Alarm Insertion Signal (AIS) at the output of each of a number of concatenated pointer processors in response to a failure at the input of any one of the pointer processors. Each of the pointer processors has an input, an output and a bidirectional terminal that is coupled to a common node. Each of the pointer processors includes circuitry coupled to the input, the output and the bidirectional terminal that causes a predetermined logic level to be asserted at the bidirectional terminal in response to the appearance of an error signal at its input and that causes an AIS to appear at its output in response to either an error signal at its input or the assertion of the predetermined logic level at its bidirectional terminal.

摘要翻译： 在诸如SONET的数据传输网络中，用于在多个级联指针处理器的每一个的输出处产生路径报警插入信号（AIS）的方法和装置，以响应于在任何一个 指针处理器。 每个指针处理器具有耦合到公共节点的输入，输出和双向终端。 每个指针处理器包括耦合到输入，输出和双向端子的电路，其响应于在其输入处出现错误信号而导致预定逻辑电平在双向端子被断言，并且导致AIS出现 在其输出处响应于其输入处的误差信号或其双向端子处的预定逻辑电平的断言。

公开(公告)号：US08176396B2

公开(公告)日：2012-05-08

申请号：US12046049

申请日：2008-03-11

申请人： Qiujie Dong ,  Andrew J. Thurston

发明人： Qiujie Dong ,  Andrew J. Thurston

IPC分类号： H03M13/00

CPC分类号： H03M13/159 ,  H03M13/1515 ,  H03M13/158

摘要： Various methods and systems for implementing Reed Solomon multiplication sections from exclusive-OR (XOR) logic are disclosed. For example, a system includes a Reed Solomon multiplication section, which includes XOR-based logic. The XOR-based logic includes an input, an output, and one or more XOR gates. A symbol X is received at the input of the XOR-based logic. The one or more XOR gates are coupled to generate a product of a power of α and X at the output, wherein α is a root of a primitive polynomial of a Reed Solomon code. Such a Reed Solomon multiplication section, which can include one or more multipliers implemented using XOR-based logic, can be included in a Reed Solomon encoder or decoder.

摘要翻译： 公开了用于从异或（XOR）逻辑实现Reed Solomon乘法部分的各种方法和系统。 例如，系统包括Reed Solomon乘法部分，其包括基于XOR的逻辑。 基于XOR的逻辑包括输入，输出和一个或多个异或门。 在基于XOR的逻辑的输入处接收符号X. 一个或多个XOR门被耦合以在输出处产生α和X的幂的乘积，其中α是里德所罗门码的原始多项式的根。 这种Reed Solomon乘法部分可以包括在Reed Solomon编码器或解码器中，该部分可以包括使用基于XOR的逻辑实现的一个或多个乘法器。

公开(公告)号：US07124064B1

公开(公告)日：2006-10-17

申请号：US09822713

申请日：2001-03-30

申请人： Andrew J. Thurston

发明人： Andrew J. Thurston

IPC分类号： G06F17/10 ,  H04B3/40

CPC分类号： G06F17/5045 ,  G06F2217/86

摘要： An apparatus and method of implementing a circuit representing a complex polynomial equation in a hardware description language (HDL) for implementing an ASIC (Application Specific Integrated Circuit) is provided. A serial circuit representing the complex polynomial equation is implemented in a software program. The serial circuit implementation is simulated to produce a plurality of parallel equations that are mapped into HDL with ASCII strings. In one embodiment, the complex polynomial equation is a Bose-Chaudhuri-Hocquenghem (BCH) code utilized in forward error correction circuitry.

摘要翻译： 提供了一种实现用于实现ASIC（专用集成电路）的硬件描述语言（HDL）中表示复数多项式方程的电路的装置和方法。 表示复数多项式方程的串行电路在软件程序中实现。 串行电路实现被模拟以产生多个并行方程，其被映射成具有ASCII字符串的HDL。 在一个实施例中，复数多项式方程是在前向纠错电路中使用的Bose-Chaudhuri-Hocquenghem（BCH）码。

公开(公告)号：US07003715B1

公开(公告)日：2006-02-21

申请号：US09822733

申请日：2001-03-30

申请人： Andrew J. Thurston

发明人： Andrew J. Thurston

IPC分类号： H03M13/00

CPC分类号： G06F7/724 ,  H03M13/152 ,  H03M13/158

摘要： An OC-192 front-end application-specific integrated circuit (ASIC) de-interleaves an OC-192 signal to create four OC-48 signals, and decodes error-correction codes embedded in each of the four OC-48 signals. The decoder generates a Bose-Chaudhuri-Hocquenghem (BCH) error polynomial in no more than 12 clock cycles. The decoder includes several Galois field multiply accumulators, and a state machine which controls the Galois field units. In the specific embodiment wherein the error-correction code is a BCH triple error-correcting code, four Galois field units are used to carry out only six equations to solve the error polynomial. The Galois field units are advantageously designed to complete a Galois field multiply/accumulate operation in a single clock cycle. The Galois field units may operate in multiply or addition pass-through modes.

摘要翻译： OC-192前端应用专用集成电路（ASIC）对OC-192信号进行解交织以产生四个OC-48信号，并解码嵌入在四个OC-48信号中的每一个中的纠错码。 解码器在不超过12个时钟周期内产生Bose-Chaudhuri-Hocquenghem（BCH）错误多项式。 解码器包括若干伽罗瓦域乘法累加器和控制伽罗瓦域单位的状态机。 在纠错码是BCH三重纠错码的具体实施例中，使用四个伽罗瓦域单元仅执行六个等式来求解误差多项式。 伽罗瓦域单元有利地设计成在单个时钟周期内完成伽罗瓦域乘法/累加运算。 伽罗瓦域单位可以以多路或多路直通模式运行。

公开(公告)号：US06735197B1

公开(公告)日：2004-05-11

申请号：US09608097

申请日：2000-06-30

申请人： Douglas E. Duschatko ,  Lane Byron Quibodeaux ,  Robert A. Hall ,  Andrew J. Thurston

发明人： Douglas E. Duschatko ,  Lane Byron Quibodeaux ,  Robert A. Hall ,  Andrew J. Thurston

IPC分类号： H04L1226

CPC分类号： H04L45/60 ,  H04J3/1611

摘要： An apparatus and method for detecting concatenation of payload data for an communication circuit is disclosed, wherein the payload data is dispersed over a first integrated circuit and one or more subsequent integrated circuits. The method and apparatus include determining whether each of the one or more subsequent integrated circuits have all channels therein designated as concatenation slaves, and communicating the determination to the first integrated circuit, the determination indicating that the one or more subsequent integrated circuits. According to an embodiment, the method and apparatus further include coupling the first integrated circuits to the one or more subsequent integrated circuits. The apparatus and method further include detecting concatenation on a first integrated circuit of the one or more integrated circuits, assigning one or more bi-directional ports coupled to the first integrated circuit as an input port, assigning each bi-directional port coupled to the one or more subsequent integrated circuits as output ports, and if any one integrated circuit among the subsequent integrated circuits includes a channel therein designated as a slave channel, providing an active high signal to the output port, the active high signal coupled to the input port of the first integrated circuit.

摘要翻译： 公开了一种用于检测用于通信电路的有效载荷数据的级联的装置和方法，其中有效载荷数据分散在第一集成电路和一个或多个后续集成电路上。 所述方法和装置包括确定所述一个或多个后续集成电路中的每一个是否具有指定为级联从站的所有信道，以及将所述确定传送到所述第一集成电路，所述确定指示所述一个或多个后续集成电路。 根据实施例，该方法和装置还包括将第一集成电路耦合到一个或多个随后的集成电路。 所述装置和方法还包括检测所述一个或多个集成电路的第一集成电路上的级联，将耦合到所述第一集成电路的一个或多个双向端口分配为输入端口，分配耦合到所述第一集成电路的每个双向端口 或更多的后续集成电路作为输出端口，并且如果后续集成电路中的任何一个集成电路包括其中指定为从属通道的通道，则向输出端口提供有效高电平信号，耦合到输入端口 第一个集成电路。

公开(公告)号：US06684350B1

公开(公告)日：2004-01-27

申请号：US09746895

申请日：2000-12-22

申请人： James T. Theodoras, II ,  Andrew J. Thurston ,  Daniel L. Chaplin

发明人： James T. Theodoras, II ,  Andrew J. Thurston ,  Daniel L. Chaplin

IPC分类号： G01R3128

CPC分类号： H04L1/24 ,  H04L1/08

摘要： A method for testing a signal path for mark ratio tolerance includes generating a varying test pattern by selecting between a first pattern and a second pattern according to a defined sequence; and sending the varying test pattern over the signal path. An apparatus disposed in a communication system includes a selection circuit for generating a varying test pattern to send over the signal path, the selection circuit generating the varying test pattern by selecting between a first pattern and a second pattern according to a select sequence signal, and a sequencer coupled to the selection circuit, the sequencer providing the select sequence signal to the selection circuit, the sequencer generating the select sequence signal according to a mode value. The mark ratio tolerance of a system can be tested, varying the data density of one portion of the signal path while maintaining a constant data density on another portion of the signal path.

摘要翻译： 用于测试用于标记比容差的信号路径的方法包括：通过根据所定义的序列在第一图案和第二图案之间选择来生成变化的测试图案; 并在信号路径上发送变化的测试模式。 设置在通信系统中的装置包括：选择电路，用于产生通过信号路径发送的变化的测试模式，所述选择电路根据选择序列信号在第一模式和第二模式之间进行选择来产生变化的测试模式;以及 定序器，耦合到所述选择电路，所述定序器将所述选择序列信号提供给所述选择电路，所述定序器根据模式值产生所述选择序列信号。 可以测试系统的标记比容差，改变信号路径的一部分的数据密度，同时在信号路径的另一部分保持恒定的数据密度。

公开(公告)号：US07447982B1

公开(公告)日：2008-11-04

申请号：US09822950

申请日：2001-03-30

申请人： Andrew J. Thurston

发明人： Andrew J. Thurston

IPC分类号： H03M13/15 ,  H03M13/33

CPC分类号： H03M13/152 ,  H03M13/158 ,  H03M13/27 ,  H03M13/6561

摘要： An OC-192 front-end application-specific integrated circuit (ASIC) de-interleaves an OC-192 signal to create four OC-48 signals, and decodes error-correction codes embedded in each of the four OC-48 signals. The decoder generates a Bose-Chaudhuri-Hocquenghem (BCH) error polynomial in no more than 12 clock cycles. The decoder includes several Galois field multiply accumulators, and a state machine which controls the Galois field units. If the error-correction code is a BCH triple error-correcting code, four Galois field units are used to carry out only six equations to solve the error polynomial. The Galois field units are advantageously designed to complete a Galois field multiply/accumulate operation in a single clock cycle. The Galois field units may operate in multiply or addition pass-through modes.

摘要翻译： OC-192前端应用专用集成电路（ASIC）对OC-192信号进行解交织以产生四个OC-48信号，并解码嵌入在四个OC-48信号中的每一个中的纠错码。 解码器在不超过12个时钟周期内产生Bose-Chaudhuri-Hocquenghem（BCH）错误多项式。 解码器包括若干伽罗瓦域乘法累加器和控制伽罗瓦域单位的状态机。 如果纠错码是BCH三重纠错码，则使用四个伽罗瓦域单位仅执行六个等式来求解误差多项式。 伽罗瓦域单元有利地设计成在单个时钟周期内完成伽罗瓦域乘法/累加运算。 伽罗瓦域单位可以以多路或多路直通模式运行。