公开(公告)号：US07471099B2

公开(公告)日：2008-12-30

申请号：US11085144

申请日：2005-03-22

申请人： Yuji Kurita ,  Hiroyoshi Yamashita ,  Hitoaki Nishiwaki

发明人： Yuji Kurita ,  Hiroyoshi Yamashita ,  Hitoaki Nishiwaki

IPC分类号： G01R31/02

CPC分类号： G01R31/3008 ,  H01L2224/05554 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45015 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3011 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2924/20753 ,  H01L2924/20754 ,  H01L2924/00012

摘要： A semiconductor device includes a plurality of signal terminals, a first power supply terminal, a second power supply terminal, a core circuit coupled to the plurality of signal terminals and the first power supply terminal, a plurality of first transistors coupled between the respective signal terminals and the second power supply terminal, and a plurality of second transistors coupled between the respective signal terminals and a ground potential, wherein the core circuit is configured to make the first transistors conductive and nonconductive alternately and make the second transistors nonconductive and conductive alternately at a time of test operation, such that one of a first transistor and a second transistor being conductive with respect to a given signal terminal requires another one of the first transistor and the second transistor to be nonconductive with respect to the given signal terminal.

摘要翻译： 半导体器件包括多个信号端子，第一电源端子，第二电源端子，耦合到多个信号端子的核心电路和第一电源端子，耦合在各个信号端子之间的多个第一晶体管 和第二电源端子，以及耦合在各个信号端子和接地电位之间的多个第二晶体管，其中，所述核心电路被配置为使所述第一晶体管交替地导通和不导电，并且使得所述第二晶体管不导通并且在 使得第一晶体管和第二晶体管中的一个相对于给定的信号端子导通，使得第一晶体管和第二晶体管中的另一个相对于给定的信号端子不导通。

公开(公告)号：US06781909B2

公开(公告)日：2004-08-24

申请号：US10373858

申请日：2003-02-27

申请人： Yuji Kurita

发明人： Yuji Kurita

IPC分类号： G11C700

CPC分类号： G11C11/406

摘要： A semiconductor memory device, which performs refreshing for data retention, provided with a power down mode that stops refreshing. The device includes a request generation circuit, which generates a refresh request signal with an oscillation signal generated by an oscillation circuit. The oscillation circuit stops generation of the oscillation signal in response to a power down mode entry signal. This reduces the current consumption of the semiconductor memory device.

公开(公告)号：US06862241B2

公开(公告)日：2005-03-01

申请号：US10617752

申请日：2003-07-14

申请人： Yuji Kurita

发明人： Yuji Kurita

IPC分类号： H01L27/04 ,  G11C7/10 ,  G11C11/401 ,  G11C11/406 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/108 ,  G11C17/16

CPC分类号： G11C7/1045

摘要： A semiconductor device operated in modes that may be re-set. The semiconductor device includes mode setting fuse circuits, each having a plurality of fuses. Each mode setting fuse circuit stores a code for setting the mode in accordance with the breakage pattern of the fuses. A fuse information selection circuit is provided with the codes from the mode setting fuse circuits. The fuse information selection circuit provides a code selection circuit with the code having the highest priority. The code selection circuit provides a decoding circuit with the high priority code. When a determination circuit receives an invalidating signal from an invalidation fuse circuit, the code selection circuit provides the decoding circuit with a code of a program circuit.

摘要翻译： 半导体器件以可重新设置的模式工作。 半导体器件包括模式设定熔丝电路，每一个具有多个保险丝。 每个模式设置熔丝电路存储用于根据保险丝的断裂模式设置模式的代码。 熔丝信息选择电路具有来自模式设定熔丝电路的代码。 保险丝信息选择电路提供具有最高优先级的代码的代码选择电路。 代码选择电路提供具有高优先级代码的解码电路。 当确定电路从无效熔丝电路接收到无效信号时，代码选择电路为解码电路提供编程电路的代码。

公开(公告)号：US20060139822A1

公开(公告)日：2006-06-29

申请号：US11085144

申请日：2005-03-22

申请人： Yuji Kurita ,  Hiroyoshi Yamashita ,  Hitoaki Nishiwaki

发明人： Yuji Kurita ,  Hiroyoshi Yamashita ,  Hitoaki Nishiwaki

IPC分类号： H02H9/00

CPC分类号： G01R31/3008 ,  H01L2224/05554 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45015 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3011 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2924/20753 ,  H01L2924/20754 ,  H01L2924/00012

摘要： A semiconductor device includes a plurality of signal terminals, a first power supply terminal, a second power supply terminal, a core circuit coupled to the plurality of signal terminals and the first power supply terminal, a plurality of first transistors coupled between the respective signal terminals and the second power supply terminal, and a plurality of second transistors coupled between the respective signal terminals and a ground potential, wherein the core circuit is configured to make the first transistors conductive and nonconductive alternately and make the second transistors nonconductive and conductive alternately at a time of test operation, such that one of a first transistor and a second transistor being conductive with respect to a given signal terminal requires another one of the first transistor and the second transistor to be nonconductive with respect to the given signal terminal.

摘要翻译： 半导体器件包括多个信号端子，第一电源端子，第二电源端子，耦合到多个信号端子的核心电路和第一电源端子，耦合在各个信号端子之间的多个第一晶体管 和第二电源端子，以及耦合在各个信号端子和接地电位之间的多个第二晶体管，其中，所述核心电路被配置为使所述第一晶体管交替地导通和不导电，并且使得所述第二晶体管不导通并且在 使得第一晶体管和第二晶体管中的一个相对于给定的信号端子导通，使得第一晶体管和第二晶体管中的另一个相对于给定的信号端子不导通。

公开(公告)号：US5912858A

公开(公告)日：1999-06-15

申请号：US1649

申请日：1997-12-31

申请人： Hiroyoshi Tomita ,  Yuji Kurita

发明人： Hiroyoshi Tomita ,  Yuji Kurita

IPC分类号： G11C11/413 ,  G06F1/12 ,  G06F13/42 ,  G11C7/10 ,  G11C7/22 ,  G11C11/407 ,  G11C11/409 ,  H04L7/00 ,  G11C8/00 ,  G11C7/00

CPC分类号： G11C7/1093 ,  G11C7/1072 ,  G11C7/1078 ,  G11C7/22

摘要： A semiconductor memory device, to which a plurality of command signals are supplied in synchronous with a clock, comprises a plurality of input circuits, having a sampling unit for inputting said command signals and said clock and sampling said command signals in synchronous with said clock, and an output unit for outputting said sampled command signals; a command decoder for receiving the command signals output by said plurality of input circuits, decoding said plurality of command signals and generating a corresponding control signal; a memory element, which implements a variety of operational modes in response to said control signals; an output timing signal generator circuit, having a circuit architecture equivalent to at least the sampling unit of said input circuit, for sampling a predetermined signal level in synchronous with said clock, and for generating an output timing signal based on the timing of the operational delay time of said sampling unit; and wherein said input circuit outputs said sampled command signals in response to said output timing signal.

摘要翻译： 与时钟同步地供给多个命令信号的半导体存储器件包括多个输入电路，具有用于输入所述命令信号和所述时钟的采样单元，并与所述时钟同步地对所述命令信号进行采样， 以及输出单元，用于输出所述采样的指令信号; 命令解码器，用于接收由所述多个输入电路输出的命令信号，解码所述多个命令信号并产生相应的控制信号; 存储元件，其响应于所述控制信号实现各种操作模式; 输出定时信号发生器电路，具有与至少所述输入电路的采样单元相当的电路结构，用于与所述时钟同步地采样预定信号电平，并且用于基于所述操作延迟的定时产生输出定时信号 所述采样单元的时间; 并且其中所述输入电路响应于所述输出定时信号而输出所述采样的指令信号。

公开(公告)号：US08035640B2

公开(公告)日：2011-10-11

申请号：US11727850

申请日：2007-03-28

申请人： Norimasa Aoyama ,  Yuji Kurita ,  Katsumi Ando

发明人： Norimasa Aoyama ,  Yuji Kurita ,  Katsumi Ando

IPC分类号： G06T17/00

CPC分类号： G06K9/00288 ,  G06K9/00208 ,  G06K9/6255

摘要： A 3-dimensional face data restoring and collating system includes a 2-dimension face image storage unit configured to store a plurality of 2-dimensional face images of persons, and a 3-dimensional face restored shape storage unit. A 3-dimensional face shape restoring unit restores a 3-dimensional face shape data from one of the plurality of 2-dimensional face images for a target one of the persons based on a 3-dimensional reference face shape data, and stores the 3-dimensional restored face shape data in the 3-dimensional face restored shape storage unit.

摘要翻译： 三维面部数据恢复和对照系统包括被配置为存储人的多个二维脸部图像的二维面部图像存储单元和三维面部恢复形状存储单元。 三维面部形状恢复单元基于三维参考面部形状数据，从多个二维人脸图像中的一个人脸图像中恢复3维脸部形状数据，并存储3维脸部形状数据， 三维面恢复形状存储单元中的三维恢复的面部形状数据。

公开(公告)号：US20070229499A1

公开(公告)日：2007-10-04

申请号：US11727850

申请日：2007-03-28

申请人： Norimasa Aoyama ,  Yuji Kurita ,  Katsumi Ando

发明人： Norimasa Aoyama ,  Yuji Kurita ,  Katsumi Ando

IPC分类号： G06T17/00

CPC分类号： G06K9/00288 ,  G06K9/00208 ,  G06K9/6255

摘要： A 3-dimensional face data restoring and collating system includes a 2-dimension face image storage unit configured to store a plurality of 2-dimensional face images of persons, and a 3-dimensional face restored shape storage unit. A 3-dimensional face shape restoring unit restores a 3-dimensional face shape data from one of the plurality of 2-dimensional face images for a target one of the persons based on a 3-dimensional reference face shape data, and stores the 3-dimensional restored face shape data in the 3-dimensional face restored shape storage unit.

摘要翻译： 三维面部数据恢复和对照系统包括被配置为存储人的多个二维脸部图像的二维面部图像存储单元和三维面部恢复形状存储单元。 三维面部形状恢复单元基于三维参考面部形状数据，从多个二维人脸图像中的一个人脸图像中恢复3维脸部形状数据，并存储3维脸部形状数据， 三维面恢复形状存储单元中的三维恢复的面部形状数据。

公开(公告)号：US6147915A

公开(公告)日：2000-11-14

申请号：US296547

申请日：1999-04-22

申请人： Makoto Yanagisawa ,  Kazuyuki Kanazashi ,  Yuji Kurita

发明人： Makoto Yanagisawa ,  Kazuyuki Kanazashi ,  Yuji Kurita

IPC分类号： G11C7/10 ,  G11C7/22 ,  G11C8/10 ,  G11C8/18 ,  G11C7/00 ,  G11C8/00

CPC分类号： G11C8/10 ,  G11C7/1045 ,  G11C7/1072 ,  G11C7/22 ,  G11C8/18 ,  G11C2207/108

摘要： A semiconductor integrated circuit includes a plurality of circuits operating in parallel in accordance with a timing signal and having an enabled state and a disabled state, a control circuit setting each of the plurality of circuits to the enable state or the disabled state in accordance with an operation mode, and a timing adjustment circuit which adjusts the timing signal in accordance with a number of circuits which are in the enabled state.

摘要翻译： 半导体集成电路包括根据定时信号并行操作并具有使能状态和禁用状态的多个电路，控制电路将多个电路中的每一个设置为使能状态或禁用状态，根据 操作模式，以及定时调整电路，其根据处于使能状态的电路的数量来调整定时信号。