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    Mechanism for synchronizing multiple skewed source-synchronous data channels with automatic initialization feature
    11.
    发明授权
    Mechanism for synchronizing multiple skewed source-synchronous data channels with automatic initialization feature 失效
    同步多个偏斜源同步数据通道与自动初始化功能的机制

    公开(公告)号：US06636955B1

    公开(公告)日：2003-10-21

    申请号：US09652480

    申请日：2000-08-31

    Applicant: Richard E. Kessler ,  Peter J. Bannon ,  Maurice B. Steinman ,  Scott E. Breach ,  Allen J. Baum ,  Gregg A. Bouchard

    Inventor： Richard E. Kessler ,  Peter J. Bannon ,  Maurice B. Steinman ,  Scott E. Breach ,  Allen J. Baum ,  Gregg A. Bouchard

    IPC: G06F1200

    CPC classification number: G06F13/1689

    Abstract: A computer system has a memory controller that includes read buffers coupled to a plurality of memory channels. The memory controller advantageously eliminates the inter-channel skew caused by memory modules being located at different distances from the memory controller. The memory controller preferably includes a channel interface and synchronization logic circuit for each memory channel. This circuit includes read and write buffers and load and unload pointers for the read buffer. Unload pointer logic generates the unload pointer and load pointer logic generates the load pointer. The pointers preferably are free-running pointers that increment in accordance with two different clock signals. The load pointer increments in accordance with a clock generated by the memory controller but that has been routed out to and back from the memory modules. The unload pointer increments in accordance with a clock generated by the computer system itself. Because the trace length of each memory channel may differ, the time that it takes for a memory module to provide read data back to the memory controller may differ for each channel. The “skew” is defined as the difference in time between when the data arrives on the earliest channel and when data arrives on the latest channel. During system initialization, the pointers are synchronized. After initialization, the pointers are used to load and unload the read buffers in such a way that the effects of inner-channel skew is eliminated.

    Abstract translation: 计算机系统具有存储器控制器，其包括耦合到多个存储器通道的读取缓冲器。 存储器控制器有利地消除由存储器模块位于与存储器控制器不同的距离处引起的通道间偏移。 存储器控制器优选地包括用于每个存储器通道的通道接口和同步逻辑电路。 该电路包括读取和写入缓冲区，读取缓冲区的加载和卸载指针。 卸载指针逻辑生成卸载指针，加载指针逻辑生成加载指针。 指针优选地是根据两个不同的时钟信号递增的自由运行指针。 负载指针根据由存储器控制器产生的时钟增加，但是已经被引出到存储器模块和从存储器模块返回。 卸载指针根据计算机系统本身产生的时钟增加。 因为每个存储器通道的迹线长度可能不同，所以存储器模块将读数据提供给存储器控制器所花费的时间可能对于每个通道而言可能不同。 “偏斜”被定义为数据到达最早通道时和数据到达最新通道之间的时间差。 在系统初始化期间，指针是同步的。 初始化之后，这些指针用于加载和卸载读取缓冲区，从而消除内部信道偏移的影响。

    System and method to reduce memory access latencies using selective replication across multiple memory ports
    14.
    发明授权
    System and method to reduce memory access latencies using selective replication across multiple memory ports 有权
    使用多个内存端口选择性复制来减少内存访问延迟的系统和方法

    公开(公告)号：US08560757B2

    公开(公告)日：2013-10-15

    申请号：US13280738

    申请日：2011-10-25

    Applicant: Jeffrey Pangborn ,  Gregg A. Bouchard ,  Rajan Goyal ,  Richard E. Kessler

    Inventor： Jeffrey Pangborn ,  Gregg A. Bouchard ,  Rajan Goyal ,  Richard E. Kessler

    IPC: G06F12/00

    CPC classification number: G06F12/1018 ,  G06F12/0292 ,  G06F12/06 ,  G06F2212/174 ,  G06F2212/2532

    Abstract: In one embodiment, a system includes memory ports distributed into subsets identified by a subset index, where each memory port has an individual wait time based on a respective workload. The system further comprises a first address hashing unit configured to receive a read request including a virtual memory address associated with a replication factor and referring to graph data. The first address hashing unit translates the replication factor into a corresponding subset index based on the virtual memory address, and converts the virtual memory address to a hardware based memory address referring to graph data in the memory ports within a subset indicated by the corresponding subset index. The system further comprises a memory replication controller configured to direct read requests to the hardware based address to the one of the memory ports within the subset indicated by the corresponding subset index with a lowest individual wait time.

    Abstract translation: 在一个实施例中，系统包括分布到由子集索引识别的子集中的存储器端口，其中每个存储器端口基于相应的工作负载具有单独的等待时间。 该系统还包括第一地址哈希单元，其被配置为接收包括与复制因子相关联的虚拟存储器地址并参考图形数据的读取请求。 第一地址散列单元基于虚拟存储器地址将复制因子转换为相应的子集索引，并且参考由相应子集索引指示的子集内的存储器端口中的图形数据将虚拟存储器地址转换为基于硬件的存储器地址 。 该系统还包括存储器复制控制器，其被配置为将读取请求引导到基于硬件的地址到具有最低个人等待时间的相应子集索引指示的子集内的存储器端口之一。

    SYSTEM AND METHOD TO REDUCE MEMORY ACCESS LATENCIES USING SELECTIVE REPLICATION ACROSS MULTIPLE MEMORY PORTS
    16.
    发明申请
    SYSTEM AND METHOD TO REDUCE MEMORY ACCESS LATENCIES USING SELECTIVE REPLICATION ACROSS MULTIPLE MEMORY PORTS 有权
    使用多个存储器端口选择性复制来减少存储器访问延迟的系统和方法

    公开(公告)号：US20130103904A1

    公开(公告)日：2013-04-25

    申请号：US13280738

    申请日：2011-10-25

    Applicant: Jeffrey Pangborn ,  Gregg A. Bouchard ,  Rajan Goyal ,  Richard E. Kessler

    Inventor： Jeffrey Pangborn ,  Gregg A. Bouchard ,  Rajan Goyal ,  Richard E. Kessler

    IPC: G06F12/10 ,  G06F12/00

    CPC classification number: G06F12/1018 ,  G06F12/0292 ,  G06F12/06 ,  G06F2212/174 ,  G06F2212/2532

    Abstract: In one embodiment, a system comprises multiple memory ports distributed into multiple subsets, each subset identified by a subset index and each memory port having an individual wait time. The system further comprises a first address hashing unit configured to receive a read request including a virtual memory address associated with a replication factor, and referring to graph data. The first address hashing unit translates the replication factor into a corresponding subset index based on the virtual memory address, and converts the virtual memory address to a hardware based memory address that refers to graph data in the memory ports within a subset indicated by the corresponding subset index. The system further comprises a memory replication controller configured to direct read requests to the hardware based address to the one of the memory ports within the subset indicated by the corresponding subset index with a lowest individual wait time.

    Abstract translation: 在一个实施例中，系统包括分布到多个子集中的多个存储器端口，每个子集由子集索引标识，每个存储器端口具有单独的等待时间。 该系统还包括第一地址哈希单元，其被配置为接收包括与复制因子相关联的虚拟存储器地址的读取请求，并且参考图形数据。 第一地址散列单元基于虚拟存储器地址将复制因子转换为对应的子集索引，并将虚拟存储器地址转换为基于硬件的存储器地址，该存储器地址涉及由相应子集指示的子集内的存储器端口中的图形数据 指数。 该系统还包括存储器复制控制器，其被配置为将读取请求引导到基于硬件的地址到具有最低个人等待时间的相应子集索引指示的子集内的存储器端口之一。

    IPsec performance optimization
    19.
    发明授权
    IPsec performance optimization 有权
    IPsec性能优化

    公开(公告)号：US07814310B2

    公开(公告)日：2010-10-12

    申请号：US10411967

    申请日：2003-04-12

    Applicant: Gregg A. Bouchard ,  Richard E. Kessler ,  Muhammad R. Hussain

    Inventor： Gregg A. Bouchard ,  Richard E. Kessler ,  Muhammad R. Hussain

    IPC: H04L29/06

    CPC classification number: H04L63/0485 ,  H04L63/1466 ,  H04L63/164

    Abstract: A method and apparatus for optimizing IPsec processing by providing execution units with windowing data during prefetch and managing coherency of security association data by management of security association accesses. Providing execution units with windowing data allows initial parallel processing of IPsec packets. The security association access ordering apparatus serializes access to the dynamic section of security association data according to packet order arrival while otherwise allowing parallel processing of the IPsec packet by multiple execution units in a security processor.

    Abstract translation: 一种通过在预取期间向执行单元提供窗口数据并通过管理安全关联访问来管理安全关联数据的一致性来优化IPsec处理的方法和装置。 为执行单元提供窗口数据允许IPsec数据包的初始并行处理。 安全关联访问排序装置根据分组顺序序列化对安全关联数据的动态部分的访问，而另外允许在安全处理器中由多个执行单元并行处理IPsec分组。

    Computer architecture and system for efficient management of bi-directional bus
    20.
    发明授权
    Computer architecture and system for efficient management of bi-directional bus 有权
    用于双向总线高效管理的计算机架构和系统

    公开(公告)号：US06920512B2

    公开(公告)日：2005-07-19

    申请号：US10780395

    申请日：2004-02-17

    Applicant: Maurice B. Steinman ,  Richard E. Kessler ,  Gregg A. Bouchard

    Inventor： Maurice B. Steinman ,  Richard E. Kessler ,  Gregg A. Bouchard

    IPC: G06F13/40 ,  G06F13/00

    CPC classification number: G06F13/4059

    Abstract: An efficient system and method for managing reads and writes on a bi-directional bus to optimize bus performance while avoiding bus contention and avoiding read/write starvation. In particular, by intelligently managing reads and writes on a bi-directional bus, bus latency can be reduced while still ensuring no bus contention or read/write starvation. This is accomplished by utilizing bus streaming control logic, separate queues for reads and writes, and a simple 2 to 1 mux.

    Abstract translation: 一种有效的系统和方法，用于管理双向总线上的读取和写入，以优化总线性能，同时避免总线争用并避免读取/写入饥饿。 特别地，通过智能地管理双向总线上的读取和写入，可以减少总线延迟，同时仍然确保没有总线争用或读取/写入饥饿。 这是通过利用总线流控制逻辑，单独的队列读取和写入以及简单的2到1多路复用来实现的。

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