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    Hermetic package for an electronic device
    11.
    发明授权
    Hermetic package for an electronic device 失效
    用于电子设备的密封包装

    公开(公告)号：US5245136A

    公开(公告)日：1993-09-14

    申请号：US757747

    申请日：1991-09-11

    申请人： Dudley A. Chance ,  David B. Goland ,  Ho-Ming Tong

    发明人： Dudley A. Chance ,  David B. Goland ,  Ho-Ming Tong

    IPC分类号： H01L21/48 ,  H01L21/50

    CPC分类号： H01L21/486 ,  H01L21/4807 ,  H01L21/50 ,  Y10S428/901 ,  Y10T428/252

    摘要： A hermetic package for an electronic device is manufactured by providing a green glass ceramic body with a green via to produce a workpiece. The workpiece is sintered at a temperature at or above 500.degree. C., while compressing the workpiece at a pressure at or above 100 pounds per square inch, so as to obtain a hermetic package. The green via comprises a mixture of copper and a glass ceramic material with a sufficient volume of glass to produce a hermetic package, yet with sufficient copper to have a suitable electrical conductivity.The hermetic package thus produced comprises a sintered glass ceramic body having an electrically conductive sintered via which is hermetically bonded to the glass ceramic body and which comprises a mixture of an electrically conductive material and a glass ceramic material. The electrically conductive material forms at most 50 volume percent of the via.The workpiece may be sintered in a sintering fixture having a frame and a compensating insert. The compensating insert and frame bound a sintering chamber for accommodating the workpiece. By providing a frame having a thermal expansion coefficient greater than that of the workpiece, and by providing a compensating insert having a thermal expansion coefficient greater than that of the frame, a close fit can be assured between the workpiece and the sintering fixture over a large range of temperatures.

    摘要翻译： 通过提供具有绿色通孔的绿色玻璃陶瓷体以制造工件来制造用于电子设备的气密封装。 将工件在等于或高于500℃的温度下烧结，同时在100磅/平方英寸的压力下压缩工件，以获得气密封装。 绿色通孔包括具有足够体积的玻璃的铜和玻璃陶瓷材料的混合物以产生气密封装，但是具有足够的铜以具有合适的导电性。 如此制造的密封包装包括具有导电烧结通孔的烧结玻璃陶瓷体，其通过气密地结合到玻璃陶瓷体并且包括导电材料和玻璃陶瓷材料的混合物。 导电材料形成通孔的至多50体积％。 工件可以在具有框架和补偿插入件的烧结夹具中烧结。 补偿插入物和框架结合用于容纳工件的烧结室。 通过提供具有大于工件的热膨胀系数的热膨胀系数的框架，并且通过提供具有大于框架的热膨胀系数的热膨胀系数的补偿插入件，可以在大的工件和烧结夹具之间确保紧密配合 温度范围

    Electrolytic printing head
    12.
    发明授权
    Electrolytic printing head 失效
    电解打印头

    公开(公告)号：US4539576A

    公开(公告)日：1985-09-03

    申请号：US562501

    申请日：1983-12-16

    申请人： Dudley A. Chance ,  Michael Sampogna

    发明人： Dudley A. Chance ,  Michael Sampogna

    IPC分类号： B41J2/385 ,  B41J2/425 ,  G01D15/06

    CPC分类号： B41J2/3855 ,  B41J2/425

    摘要： An electrolytic print head comprises a plurality of styli (16, 18) between electrically insulative laminae (38, 42, 48, 38', 42', 48') which space the styli from planar reference electrodes (20, 22, 24). The styli and reference electrodes are fabricated of a mixture of ruthenium dioxide and corrosion resistant glass, and the insulative laminae are fabricated of corrosion resistant glass. The method of manufacture of the print head facilitates use of styli and reference electrodes requiring high temperature processing prior to deposition of metal conductor tracks for the styli and reference electrodes.

    摘要翻译： 电解打印头包括多个位于电绝缘层（38,42,48,38'，42'，48'）之间的测针（16,18），其将测针与平面参考电极（20,22,24）间隔开。 测针和参比电极由二氧化钌和耐腐蚀玻璃的混合物制成，绝缘层由耐腐蚀玻璃制成。 打印头的制造方法有助于在沉积用于测针和参考电极的金属导体轨迹之前使用需要高温处理的测针和参考电极。

    LSI Chip carrier with buried repairable capacitor with low inductance leads
    14.
    发明授权
    LSI Chip carrier with buried repairable capacitor with low inductance leads 失效
    具有埋入可修复电容器的LSI芯片载体，低电感引线

    公开(公告)号：US4453176A

    公开(公告)日：1984-06-05

    申请号：US336485

    申请日：1981-12-31

    申请人： Dudley A. Chance ,  Gerard V. Kopcsay

    发明人： Dudley A. Chance ,  Gerard V. Kopcsay

    IPC分类号： H05K3/46 ,  H01L23/538 ,  H01L23/64 ,  H05K1/00 ,  H05K1/16 ,  H01L27/02

    CPC分类号： H01L23/5383 ,  H01L23/642 ,  H01L2224/16 ,  H01L2924/09701 ,  H05K1/0286 ,  H05K1/162

    摘要： A carrier for LSI chips includes a built-in capacitor structure in the carrier. The capacitor is located beneath the chip with the plates of the capacitor parallel to the chip mounting surface or at right angles to the chip mounting surface. The capacitor is formed by assembling an array of capacitive segments together to form the first one of the plates of a capacitor with the other plate spanning a plurality of the segments of the first plate. Each of the segments of the first plate includes a set of conductive via lines which extend up to a severable link on the chip mounting surface. The severable via is cut by means of a laser beam or the like when the capacitor must be repaired by deleting a defective segment of the capacitor. Preferably, the structure includes a pair of parallel conductive charge redistribution planes above and below the capacitor plates with connections to the respective plates providing a low inductance structure achieved by providing a current distribution which results in cancellation of magnetic flux. The lower redistribution plane is preferably connected directly to the lower capacitor plate. The upper redistribution plane is preferably connected to the segments of the first capacitor plate by means of the vias which extend first to the chip mounting surface and then down to the redistribution plane which has connections to the chip mounting pads.

    摘要翻译： 用于LSI芯片的载体包括载体中的内置电容器结构。 电容器位于芯片下方，电容器的平板平行于芯片安装表面或与芯片安装表面成直角。 电容器通过将电容性段的阵列组装在一起形成电容器的第一板，而另一个板跨越第一板的多个段。 第一板的每个段包括一组导电通孔线，其延伸到芯片安装表面上的可分离的连接。 当电容器必须通过删除电容器的缺陷部分进行修理时，可以通过激光束等切割可分离的通孔。 优选地，该结构包括在电容器板之上和之下的一对平行的导电电荷再分配平面，其中连接到相应的板提供通过提供导致磁通消除的电流分布而实现的低电感结构。 下再分布平面优选直接连接到下电容器板。 上再分布平面优选通过首先连接到芯片安装表面然后向下延伸到具有与芯片安装焊盘连接的再分布平面的通孔连接到第一电容器板的段。

    Capacitive chip carrier and multilayer ceramic capacitors
    15.
    发明授权
    Capacitive chip carrier and multilayer ceramic capacitors 失效
    电容芯片载体和多层陶瓷电容器

    公开(公告)号：US4349862A

    公开(公告)日：1982-09-14

    申请号：US176949

    申请日：1980-08-11

    申请人： Christopher H. Bajorek ,  Dudley A. Chance ,  Chung W. Ho

    发明人： Christopher H. Bajorek ,  Dudley A. Chance ,  Chung W. Ho

    IPC分类号： H01L23/12 ,  H01G4/12 ,  H01G4/38 ,  H01L23/15 ,  H01L23/538 ,  H01L23/64 ,  H01L25/00 ,  H01L27/00 ,  H05K1/03 ,  H05K1/09 ,  H05K1/16 ,  H05K3/46

    CPC分类号： H01L23/642 ,  H01L23/15 ,  H01L23/5383 ,  H05K1/162 ,  H01L2224/16 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01046 ,  H01L2924/01068 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/15311 ,  H01L2924/15312 ,  H05K1/0306 ,  H05K1/092 ,  H05K2201/09763 ,  H05K3/4611 ,  H05K3/4629

    摘要： A chip carrier system for supporting electronic semiconductor chips is provided with a matched coefficient of thermal expansion as well as a high value of capacitance. The carrier provides both mechanical and electrical connections to the chip. A small sized interposer for a silicon chip possesses high capacitance. An array of dot capacitors is formed between laminated layers of ceramic material. In some cases, conductive surfaces are provided on the upper and lower surfaces of a thin film of ceramic material in which dielectric bodies are interspersed in an array of openings therein. The resultant ceramic dielectric combination has a coefficient of thermal expansion which matches the coefficient of thermal expansion of the silicon chip and the substrate thereby relieving stress upon the solder ball joints between the interposer and both the chip and the substrate. This minimizes the mechanical stress upon the solder ball joints during thermal cycling of the structure. Alternatively, an array of multilayer ceramic capacitors has an array of dielectric bodies located within holes in ceramic layers between capacitor plates, or entire arrays of capacitors are formed in the space between ceramic sheets.

    摘要翻译： 用于支持电子半导体芯片的芯片载体系统具有匹配的热膨胀系数以及高电容值。 载体提供与芯片的机械和电气连接。 用于硅芯片的小尺寸插入器具有高电容。 在陶瓷材料的层压层之间形成点阵电容器阵列。 在一些情况下，导电表面设置在陶瓷材料薄膜的上表面和下表面上，其中介电体散布在其中的开口阵列中。 所得到的陶瓷电介质组合具有与硅芯片和基板的热膨胀系数匹配的热膨胀系数，从而缓解了插入件与芯片和基板之间的焊球接头的应力。 这最小化了结构热循环过程中焊球接头处的机械应力。 或者，多层陶瓷电容器阵列具有位于电容器板之间的陶瓷层中的孔内的介电体阵列，或在陶瓷片之间的空间中形成整个电容器阵列。

    Integrated circuit carriers and a method for making engineering changes in said carriers
    16.
    发明授权
    Integrated circuit carriers and a method for making engineering changes in said carriers 失效
    集成电路载体和用于在所述载波中进行工程变化的方法

    公开(公告)号：US5155577A

    公开(公告)日：1992-10-13

    申请号：US638305

    申请日：1991-01-07

    申请人： Dudley A. Chance ,  Timothy R. Dinger ,  David P. Lapotin ,  Walter V. Vilkelis

    发明人： Dudley A. Chance ,  Timothy R. Dinger ,  David P. Lapotin ,  Walter V. Vilkelis

    IPC分类号： H01L21/48 ,  H01L23/538 ,  H05K1/11 ,  H05K3/22

    CPC分类号： H01L23/5382 ,  H01L21/485 ,  H01L2924/0002

    摘要： An integrated circuit carrier comprising a modular substrate having an upper surface, a multitude of electrically conducting device terminals on the upper surface of the substrate, a multitude of electrically conducting engineering change pads also on the upper surface of the substrate, and an engineering change network to form a unique electrical connection between each of an arbitrary subset of the device terminals and each of an arbitrary subset of the engineering change pads. The engineering change network includes a multitude of connecting pads, and a multitude of first, second, and third conductive leads or wires, and each of the connecting pads includes first and second spaced apart sections.

    摘要翻译： 一种集成电路载体，其包括具有上表面的模块化基板，在基板的上表面上的多个导电器件端子，还在基板的上表面上的多个导电工程改变焊盘，以及工程变更网络 以在设备终端的任意子集和工程变更焊盘的任意子集中的每一个之间形成唯一的电连接。 工程变更网络包括多个连接焊盘和多个第一，第二和第三导电引线或电线，并且每个连接焊盘包括第一和第二间隔开的部分。