公开(公告)号：US09502302B2

公开(公告)日：2016-11-22

申请号：US14512700

申请日：2014-10-13

Applicant: STMicroelectronics, Inc. ,  GlobalFoundries Inc ,  International Business Machines Corporation

Inventor： Qing Liu ,  Ruilong Xie ,  Chun-Chen Yeh

IPC: H01L21/8234 ,  H01L29/423

CPC classification number: H01L29/42376 ,  H01L21/82345 ,  H01L21/823456 ,  H01L27/088 ,  H01L29/42372 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/78

Abstract: Dummy gates are removed from a pre-metal layer to produce a first opening (with a first length) and a second opening (with a second length longer than the first length). Work function metal for a metal gate electrode is provided in the first and second openings. Tungsten is deposited to fill the first opening and conformally line the second opening, thus leaving a third opening. The thickness of the tungsten layer substantially equals the length of the first opening. The third opening is filled with an insulating material. The tungsten is then recessed in both the first and second openings using a dry etch to substantially a same depth from a top surface of the pre-metal layer to complete the metal gate electrode. Openings left following the recess operation are then filled with a dielectric material forming a cap on the gate stack which includes the metal gate electrode.

Abstract translation: 从预金属层去除虚拟门以产生具有第一长度的第一开口和第二开口（具有长于第一长度的第二长度）。 用于金属栅电极的功函数金属设置在第一和第二开口中。 沉积钨以填充第一开口并保形地排列第二开口，从而留下第三个开口。 钨层的厚度基本上等于第一开口的长度。 第三个开口填充绝缘材料。 然后使用干蚀刻将钨从第一和第二开口凹入到与金属前层的顶表面基本相同的深度以完成金属栅电极。 然后在凹槽操作之后留下的开口填充有在包括金属栅电极的栅堆叠上形成盖的电介质材料。

公开(公告)号：US09496185B2

公开(公告)日：2016-11-15

申请号：US14670800

申请日：2015-03-27

Applicant: International Business Machines Corporation ,  GLOBALFOUNDRIES, Inc. ,  STMICROELECTRONICS, INC.

Inventor： Xiuyu Cai ,  Qing Liu ,  Ruilong Xie ,  Chun-Chen Yeh

IPC: H01L27/12 ,  H01L21/84 ,  H01L29/78

CPC classification number: H01L21/845 ,  H01L27/1211 ,  H01L29/7849

Abstract: Fabricating a semiconductor device includes providing a strained semiconductor material (SSM) layer disposed on a dielectric layer, forming a first plurality of fins on the SSOI structure, at least one fin of the first plurality of fins is in a nFET region and at least one fin is in a pFET region, etching portions of the dielectric layer under portions of the SSM layer of the at least one fin in the pFET region, filling areas cleared by the etching, forming a second plurality of fins from the at least one fin in the nFET region such that each fin comprises a portion of the SSM layer disposed on the dielectric layer, and forming a third plurality of fins from the at least one fin in the pFET region such that each fin comprises a portion of the SSM layer disposed on a flowable oxide.

Abstract translation: 制造半导体器件包括提供设置在电介质层上的应变半导体材料（SSM）层，在SSOI结构上形成第一多个鳍片，第一组多个鳍片中的至少一个鳍片在nFET区域中，并且至少一个 鳍状物在pFET区域中，在pFET区域中的至少一个鳍片的SSM层的部分之下蚀刻介电层的部分，通过蚀刻清除的填充区域，从至少一个鳍片形成第二多个鳍片 所述nFET区域使得每个鳍片包括设置在所述电介质层上的所述SSM层的一部分，以及从所述pFET区域中的所述至少一个翅片形成第三多个翅片，使得每个翅片包括设置在所述SSM层上的部分 可流动的氧化物。

公开(公告)号：US20160293761A1

公开(公告)日：2016-10-06

申请号：US15180860

申请日：2016-06-13

Applicant: International Business Machines Corporation ,  GLOBALFOUNDRIES INC. ,  STMICROELECTRONICS, INC.

Inventor： Qing Liu ,  Xiuyu Cai ,  Ruilong Xie ,  Chun-chen Yeh

IPC: H01L29/78 ,  H01L29/161 ,  H01L27/12 ,  H01L29/165 ,  H01L29/10 ,  H01L29/06 ,  H01L29/08 ,  H01L29/16

CPC classification number: H01L27/1211 ,  G06N3/04 ,  G10L15/16 ,  H01L21/28132 ,  H01L21/823437 ,  H01L21/823468 ,  H01L29/0649 ,  H01L29/1037 ,  H01L29/365 ,  H01L29/41775 ,  H01L29/41783 ,  H01L29/41791 ,  H01L29/66553 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785 ,  H01L2029/7858 ,  H01L2924/13067

Abstract: Techniques and structures for controlling etch-back of a finFET fin are described. One or more layers may be deposited over the fin and etched. Etch-back of a planarization layer may be used to determine a self-limited etch height of one or more layers adjacent the fin and a self-limited etch height of the fin. Strain-inducing material may be formed at regions of the etched fin to induce strain in the channel of a finFET.

公开(公告)号：US09460969B1

公开(公告)日：2016-10-04

申请号：US14669055

申请日：2015-03-26

Applicant: International Business Machines Corporation ,  Globalfoundries, Inc. ,  STMicroelectronics, Inc.

Inventor： Xiuyu Cai ,  Qing Liu ,  Ruilong Xie ,  Chun-Chen Yeh

IPC: H01L21/66 ,  H01L21/8238 ,  H01L21/768 ,  H01L21/308 ,  H01L21/306

CPC classification number: H01L21/823871 ,  H01L21/30625 ,  H01L21/3085 ,  H01L21/82385 ,  H01L22/12 ,  H01L22/30

Abstract: A technique relates to fabricating a macro for measurements utilized in dual spacer, dual epitaxial transistor devices. The macro is fabricated according to a fabrication process. The macro is a test layout of a semiconductor structure having n-p bumps at junctions between NFET areas and PFET areas. Optical critical dimension (OCD) spectroscopy is performed to obtain the measurements of the n-p bumps on the macro. An amount of chemical mechanical polishing is determined to remove the n-p bumps on the macro based on the measurements of the n-p bumps on the macro. Chemical mechanical polishing is performed to remove the n-p bumps on the macro. The amount previously determined for the macro is utilized to perform chemical mechanical polishing for each of the dual spacer, dual epitaxial layer transistor devices having been fabricated under the fabrication process of the macro in which the fabrication process produced the n-p bumps.

Abstract translation: 技术涉及制造用于双间隔物，双外延晶体管器件中的测量的宏。 宏是根据制造工艺制造的。 该宏是在NFET区域和PFET区域之间的结处具有n-p个凸起的半导体结构的测试布局。 执行光临界尺度（OCD）光谱以获得宏观上的n-p凸块的测量。 基于宏观上的n-p凸块的测量，确定了一定量的化学机械抛光以去除宏观上的n-p凸块。 进行化学机械抛光以除去宏观上的n-p凸块。 先前为宏确定的量用于对在制造工艺产生n-p个凸块的宏的制造过程中制造的每个双间隔物，双外延层晶体管器件进行化学机械抛光。

公开(公告)号：US20160260741A1

公开(公告)日：2016-09-08

申请号：US15155904

申请日：2016-05-16

Applicant: STMicroelectronics, Inc. ,  International Business Machines Corporation ,  GlobalFoundries Inc

Inventor： Qing Liu ,  Chun-Chen Yeh ,  Ruilong Xie ,  Xiuyu Cai ,  Kejia Wang

IPC: H01L27/12 ,  H01L27/088 ,  H01L21/311 ,  H01L29/78 ,  H01L29/66 ,  H01L21/02

CPC classification number: H01L27/1211 ,  H01L21/0217 ,  H01L21/02247 ,  H01L21/31111 ,  H01L27/0886 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: In forming a finFET, a selective nitridation process is used during spacer formation on the gate to support a finer fin pitch than could be achieved using traditional spacer deposition processes. The spacer formation may also allow precise control over formation of source and drain junctions.

Abstract translation: 在形成finFET时，在栅极的间隔物形成期间使用选择性氮化工艺，以支持比使用传统间隔物沉积工艺可获得更细的翅片间距。 间隔物形成还可以允许对源极和漏极结的形成的精确控制。

公开(公告)号：US09437504B2

公开(公告)日：2016-09-06

申请号：US14802407

申请日：2015-07-17

Applicant: STMicroelectronics, Inc. ,  International Business Machines Corporation

Inventor： Nicolas Loubet ,  Prasanna Khare ,  Qing Liu ,  Balasubramanian Pranatharthiharan ,  Shom Ponoth

IPC: H01L21/8234 ,  H01L21/84 ,  H01L21/8238 ,  H01L21/762 ,  H01L29/66 ,  H01L21/02 ,  H01L27/12

CPC classification number: H01L21/845 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/76224 ,  H01L21/823821 ,  H01L21/823878 ,  H01L27/1211 ,  H01L29/6653 ,  H01L29/6656

Abstract: On a first semiconductor material substrate, an overlying sacrificial layer formed of a second semiconductor material is deposited. In a first region, a first semiconductor material region is formed over the sacrificial layer. In a second region, a second semiconductor material region is formed over the sacrificial layer. The first semiconductor material region is patterned to define a first FinFET fin. The second semiconductor material region is patterned to define a second FinFET fin. The fins are each covered with a cap and sidewall spacer. The sacrificial layer formed of the second semiconductor material is then selectively removed to form an opening below each of the first and second FinFET fins (with those fins being supported by the sidewall spacers). The openings below each of the fins are then filled with a dielectric material that serves to isolate the semiconductive materials of the fins from the substrate.

Abstract translation: 在第一半导体材料基板上沉积由第二半导体材料形成的上覆牺牲层。 在第一区域中，在牺牲层上形成第一半导体材料区域。 在第二区域中，在牺牲层上形成第二半导体材料区域。 图案化第一半导体材料区域以限定第一FinFET鳍片。 图案化第二半导体材料区域以限定第二FinFET鳍片。 翅片各自被盖和侧壁间隔物覆盖。 然后选择性地去除由第二半导体材料形成的牺牲层，以在第一和第二FinFET鳍片下面形成开口（这些鳍片由侧壁间隔件支撑）。 然后每个翅片下面的开口填充有用于将鳍片的半导体材料与衬底隔离的介电材料。

公开(公告)号：US20160197072A1

公开(公告)日：2016-07-07

申请号：US15073100

申请日：2016-03-17

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  STMICROELECTRONICS, INC ,  GLOBALFOUNDRIES INC.

Inventor： Qing Liu ,  Xiuyu Cai ,  Ruilong Xie ,  Chun-chen Yeh ,  Kejia Wang ,  Daniel Chanemougame

IPC: H01L27/088 ,  H01L29/161 ,  H01L29/06

CPC classification number: H01L27/0886 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/0649 ,  H01L29/161 ,  H01L29/66795

Abstract: A semiconductor device which includes: a substrate; a first set of fins above the substrate of a first semiconductor material; a second set of fins above the substrate and of a second semiconductor material different than the first semiconductor material; and an isolation region positioned between the first and second sets of fins, the isolation region having a nitride layer. The isolation region may be an isolation pillar or an isolation trench.

Abstract translation: 一种半导体器件，包括：衬底; 在第一半导体材料的衬底上方的第一组鳍; 在衬底上方的第二组鳍和不同于第一半导体材料的第二半导体材料; 以及位于所述第一和第二组翅片之间的隔离区域，所述隔离区域具有氮化物层。 隔离区可以是隔离柱或隔离沟槽。

公开(公告)号：US09385201B2

公开(公告)日：2016-07-05

申请号：US14297822

申请日：2014-06-06

Applicant: STMicroelectronics, Inc. ,  GlobalFoundries Inc ,  International Business Machines Corporation

Inventor： Qing Liu ,  Ruilong Xie ,  Chun-Chen Yeh ,  Xiuyu Cai ,  William J. Taylor

IPC: H01L21/84 ,  H01L29/417 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L21/823475 ,  H01L21/28518 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/785

Abstract: An integrated circuit transistor is formed on a substrate. A trench in the substrate is at least partially filed with a metal material to form a source (or drain) contact buried in the substrate. The substrate further includes a source (or drain) region in the substrate which is in electrical connection with the source (or drain) contact. The substrate further includes a channel region adjacent to the source (or drain) region. A gate dielectric is provided on top of the channel region and a gate electrode is provided on top of the gate dielectric. The substrate may be of the silicon on insulator (SOI) or bulk type. The buried source (or drain) contact makes electrical connection to a side of the source (or drain) region using a junction provided at a same level of the substrate as the source (or drain) and channel regions.

Abstract translation: 在基板上形成集成电路晶体管。 衬底中的沟槽至少部分地与金属材料填充以形成埋在衬底中的源极（或漏极）接触。 衬底还包括与源极（或漏极）接触电连接的衬底中的源极（或漏极）区域。 衬底还包括与源极（或漏极）区域相邻的沟道区域。 栅极电介质设置在沟道区域的顶部，栅电极设置在栅极电介质的顶部。 衬底可以是绝缘体上硅（SOI）或体积型。 埋入的源极（或漏极）接触器使用与源极（或漏极）和沟道区域在基底的相同水平处提供的接点，使得与源极（或漏极）区域的一侧电连接。

公开(公告)号：US20160190314A1

公开(公告)日：2016-06-30

申请号：US14588318

申请日：2014-12-31

Applicant: STMICROELECTRONICS, INC. ,  GLOBALFOUNDRIES Inc. ,  INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Qing Liu ,  Xiuyu Cai ,  Chun-chen Yeh ,  Ruilong Xie

IPC: H01L29/78 ,  H01L29/423 ,  H01L21/28 ,  H01L21/265 ,  H01L21/266 ,  H01L29/66 ,  H01L29/51

CPC classification number: H01L29/7855 ,  H01L21/26513 ,  H01L21/266 ,  H01L21/28141 ,  H01L29/0653 ,  H01L29/0657 ,  H01L29/41783 ,  H01L29/42356 ,  H01L29/4236 ,  H01L29/51 ,  H01L29/518 ,  H01L29/66484 ,  H01L29/66787 ,  H01L29/66795 ,  H01L29/66818 ,  H01L29/7831 ,  H01L29/785

Abstract: A vertical slit transistor includes raised source, drain, and channel regions in a semiconductor substrate. Two gate electrodes are positioned adjacent respective sidewalls of the semiconductor substrate. A dielectric material separates the gate electrodes from the source and drain regions.

Abstract translation: 垂直狭缝晶体管包括半导体衬底中的凸起的源极，漏极和沟道区。 两个栅极位于半导体衬底的相应侧壁附近。 电介质材料将栅电极与源区和漏区分开。

公开(公告)号：US20160111513A1

公开(公告)日：2016-04-21

申请号：US14984688

申请日：2015-12-30

Applicant: STMicroelectronics, Inc. ,  GlobalFoundries Inc. ,  International Business Machines Corporation

Inventor： Qing Liu ,  Ruilong Xie ,  Chun-chen Yeh ,  Xiuyu Cai

IPC: H01L29/423 ,  H01L29/165 ,  H01L29/06 ,  H01L29/16 ,  H01L29/786 ,  H01L29/66

CPC classification number: H01L29/42392 ,  B82Y10/00 ,  H01L29/0649 ,  H01L29/0673 ,  H01L29/1037 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/167 ,  H01L29/36 ,  H01L29/42364 ,  H01L29/51 ,  H01L29/518 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/66742 ,  H01L29/6681 ,  H01L29/775 ,  H01L29/785 ,  H01L29/78618 ,  H01L29/78696

Abstract: A high performance GAA FET is described in which vertically stacked silicon nanowires carry substantially the same drive current as the fin in a conventional FinFET transistor, but at a lower operating voltage, and with greater reliability. One problem that occurs in existing nanowire GAA FETs is that, when a metal is used to form the wraparound gate, a short circuit can develop between the source and drain regions and the metal gate portion that underlies the channel. The vertically stacked nanowire device described herein, however, avoids such short circuits by forming insulating barriers in contact with the source and drain regions, prior to forming the gate. Through the use of sacrificial films, the fabrication process is almost fully self-aligned, such that only one lithography mask layer is needed, which significantly reduces manufacturing costs.

Abstract translation: 描述了一种高性能GAA FET，其中垂直堆叠的硅纳米线在传统的FinFET晶体管中承载与鳍片基本上相同的驱动电流，但是在较低的工作电压下并且具有更高的可靠性。 在现有的纳米线GAA FET中出现的一个问题是当金属用于形成环绕栅极时，在源极和漏极区域之间以及在通道下方的金属栅极部分发生短路。 然而，本文所述的垂直堆叠的纳米线器件在形成栅极之前通过形成与源极和漏极区域接触的绝缘屏障来避免这种短路。 通过使用牺牲膜，制造工艺几乎完全自对准，使得仅需要一个光刻掩模层，这显着降低制造成本。