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    Semiconductor resistors formed at a lower height level in a semiconductor device comprising metal gates
    111.
    发明授权
    Semiconductor resistors formed at a lower height level in a semiconductor device comprising metal gates 有权
    在包括金属栅极的半导体器件中，在较低高度处形成半导体电阻器

    公开(公告)号：US08658509B2

    公开(公告)日：2014-02-25

    申请号：US12907731

    申请日：2010-10-19

    申请人： Ralf Richter ,  Jens Heinrich ,  Andy Wei

    发明人： Ralf Richter ,  Jens Heinrich ,  Andy Wei

    IPC分类号： H01L21/20 ,  H01L27/06

    CPC分类号： H01L29/66545 ,  H01L27/0629 ,  H01L28/20 ,  H01L29/4966 ,  H01L29/51 ,  H01L29/6659 ,  H01L29/7833

    摘要： In sophisticated semiconductor devices comprising high-k metal gate electrode structures formed on the basis of a replacement gate approach, semiconductor-based resistors may be provided without contributing to undue process complexity in that the resistor region is recessed prior to depositing the semiconductor material of the gate electrode structure. Due to the difference in height level, a reliable protective dielectric material layer is preserved above the resistor structure upon exposing the semiconductor material of the gate electrode structure and removing the same on the basis of selective etch recipes. Consequently, well-established semiconductor materials, such as polysilicon, may be used for the resistive structures in complex semiconductor devices, substantially without affecting the overall process sequence for forming the sophisticated replacement gate electrode structures.

    摘要翻译： 在包括基于替换栅极方法形成的高k金属栅极电极结构的复杂半导体器件中，可以提供基于半导体的电阻器，而不会造成过度的工艺复杂性，因为电阻器区域在沉积半导体材料 栅电极结构。 由于高度水平的差异，在暴露栅极电极结构的半导体材料并基于选择性蚀刻配方将其去除时，可靠的保护介电材料层被保留在电阻器结构之上。 因此，诸如多晶硅的公认的半导体材料可以用于复合半导体器件中的电阻结构，基本上不影响用于形成复杂的替代栅电极结构的整个工艺顺序。

    Method of reducing contamination by providing an etch stop layer at the substrate edge
    113.
    发明授权
    Method of reducing contamination by providing an etch stop layer at the substrate edge 有权
    通过在衬底边缘处提供蚀刻停止层来减少污染的方法

    公开(公告)号：US08426312B2

    公开(公告)日：2013-04-23

    申请号：US11531793

    申请日：2006-09-14

    申请人： Ralf Richter ,  Tobias Letz ,  Holger Schuehrer

    发明人： Ralf Richter ,  Tobias Letz ,  Holger Schuehrer

    IPC分类号： H01L21/461

    CPC分类号： H01L21/02087 ,  H01L21/6708 ,  H01L21/76801 ,  H01L21/76877

    摘要： By providing an etch stop layer selectively at the bevel, at least one additional wet chemical bevel etch process may be performed prior to or during the formation of a metallization layer without affecting the substrate material. Hence, the dielectric material, especially the low-k dielectric material, may be reliably removed from the bevel prior to the formation of any barrier and metal layers. The etch stop layer may be formed at an early manufacturing stage so that a bevel etch process may be performed at any desired stage of the formation of circuit elements.

    摘要翻译： 通过在斜面上选择性地设置蚀刻停止层，可以在形成金属化层之前或期间执行至少一个附加的湿化学斜面蚀刻工艺，而不影响衬底材料。 因此，在形成任何阻挡层和金属层之前，电介质材料，特别是低k电介质材料可以从斜面被可靠地移除。 蚀刻停止层可以在早期制造阶段形成，从而可以在形成电路元件的任何期望阶段执行斜面蚀刻工艺。

    Reduced topography-related irregularities during the patterning of two different stress-inducing layers in the contact level of a semiconductor device
    114.
    发明授权
    Reduced topography-related irregularities during the patterning of two different stress-inducing layers in the contact level of a semiconductor device 有权
    在半导体器件的接触电平中的两个不同的应力感应层的图案化期间减少了与地形相关的不规则性

    公开(公告)号：US08349740B2

    公开(公告)日：2013-01-08

    申请号：US12623493

    申请日：2009-11-23

    申请人： Ralf Richter

    发明人： Ralf Richter

    IPC分类号： H01L21/311

    CPC分类号： H01L21/823807 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7843

    摘要： In sophisticated semiconductor devices, stress-inducing materials may be provided above the basic transistor devices without any etch control or etch stop materials, thereby enabling an efficient de-escalation of the surface topography, in particular above field regions including closely spaced polysilicon lines. Furthermore, an additional stress-inducing material may be provided on the basis of the superior surface topography, thereby providing a highly efficient strain-inducing mechanism in performance-driven transistor elements.

    摘要翻译： 在复杂的半导体器件中，可以在基本晶体管器件上方提供应力诱导材料，而无需任何蚀刻控制或蚀刻停止材料，从而能够有效地降低表面形貌，特别是包括紧密间隔的多晶硅线的上述场区域。 此外，可以基于优异的表面形貌提供额外的应力诱导材料，从而在性能驱动的晶体管元件中提供高效的应变诱导机制。

    Cap layer removal in a high-K metal gate stack by using an etch process
    116.
    发明授权
    Cap layer removal in a high-K metal gate stack by using an etch process 有权
    通过使用蚀刻工艺在高K金属栅极堆叠中去除盖层

    公开(公告)号：US08258062B2

    公开(公告)日：2012-09-04

    申请号：US12824534

    申请日：2010-06-28

    申请人： Ralf Richter ,  Frank Seliger ,  Martin Mazur

    发明人： Ralf Richter ,  Frank Seliger ,  Martin Mazur

    IPC分类号： H01L21/302 ,  H01L21/461

    CPC分类号： H01L29/7843 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823828 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/7848

    摘要： In a replacement gate approach, the dielectric cap layers of the gate electrode structures are removed in a separate removal process, such as a plasma assisted etch process, in order to provide superior process conditions during the subsequent planarization of the interlayer dielectric material for exposing the sacrificial gate material. Due to the superior process conditions, the selective removal of the sacrificial gate material may be accomplished with enhanced uniformity, thereby also contributing to superior stability of transistor characteristics.

    摘要翻译： 在替代栅极方法中，在单独的去除工艺（例如等离子体辅助蚀刻工艺）中去除栅电极结构的电介质盖层，以便在层间电介质材料随后的平坦化期间提供优异的工艺条件， 牺牲栅材料。 由于优异的工艺条件，牺牲栅极材料的选择性去除可以通过增强的均匀性来实现，从而也有助于晶体管特性的优异的稳定性。

    SEMICONDUCTOR DEVICE AND METHOD FOR PATTERNING VERTICAL CONTACTS AND METAL LINES IN A COMMON ETCH PROCESS
    117.
    发明申请
    SEMICONDUCTOR DEVICE AND METHOD FOR PATTERNING VERTICAL CONTACTS AND METAL LINES IN A COMMON ETCH PROCESS 有权
    用于在常见蚀刻过程中绘制垂直接触和金属线的半导体器件和方法

    公开(公告)号：US20120220119A1

    公开(公告)日：2012-08-30

    申请号：US13468083

    申请日：2012-05-10

    申请人： Ralf Richter ,  Robert Seidel ,  Juergen Boemmels ,  Thomas Foltyn

    发明人： Ralf Richter ,  Robert Seidel ,  Juergen Boemmels ,  Thomas Foltyn

    IPC分类号： H01L21/768 ,  H01L21/308

    CPC分类号： H01L21/7681 ,  H01L21/76811 ,  H01L21/76816

    摘要： Interlayer connections, i.e., vertical connections, may be formed on the basis of a hard mask material, which may be positioned below, within or above an interlayer dielectric material, wherein one lateral dimension is defined by a trench mask, thereby obtaining a desired interlayer connection in a common patterning process. Furthermore, the thickness of at least certain portions of the metal lines may be adjusted with a high degree of flexibility, thereby providing the possibility of significantly reducing the overall resistivity of metal lines in metal levels, in which device performance may significantly depend on resistivity rather than parasitic capacitance.

    摘要翻译： 中间层连接（即垂直连接）可以基于硬掩模材料形成，硬掩模材料可以位于层间电介质材料的内部或之上，其中一个横向尺寸由沟槽掩模限定，从而获得所需的中间层 连接在共同的图案化过程中。 此外，金属线的至少某些部分的厚度可以以高度的柔性来调节，从而提供了显着降低金属线中金属线的整体电阻率的可能性，其中器件性能可能显着地取决于电阻率 比寄生电容。

    Method for forming a substrate contact for advanced SOI devices based on a deep trench capacitor configuration
    118.
    发明授权
    Method for forming a substrate contact for advanced SOI devices based on a deep trench capacitor configuration 有权
    基于深沟槽电容器配置的先进SOI器件形成衬底接触的方法

    公开(公告)号：US07939415B2

    公开(公告)日：2011-05-10

    申请号：US12171633

    申请日：2008-07-11

    申请人： Ralf Richter

    发明人： Ralf Richter

    IPC分类号： H01L21/331

    CPC分类号： H01L21/84 ,  H01L21/743 ,  H01L27/1087 ,  H01L27/1203

    摘要： By forming a first portion of a substrate contact in an SOI device on the basis of a trench capacitor process, the overall manufacturing process for patterning contact elements may be enhanced since the contacts may only have to extend down to the level of the semiconductor layer. Since the lower portion of the substrate contact may be formed concurrently with the fabrication of trench capacitors, complex patterning steps may be avoided which may otherwise have to be introduced when the substrate contacts are to be formed separately from contact elements connecting to the device level.

    摘要翻译： 通过基于沟槽电容器工艺在SOI器件中形成衬底接触的第一部分，可以增强用于对接触元件进行图形化的整体制造工艺，因为接触可能只能向下延伸到半导体层的水平。 由于衬底接触的下部可以与沟槽电容器的制造同时形成，所以可以避免复杂的图案化步骤，否则当衬底触点与连接到器件级别的接触元件分开形成时可能需要引入。