公开(公告)号：US11776608B2

公开(公告)日：2023-10-03

申请号：US16672722

申请日：2019-11-04

Applicant: QUALCOMM Incorporated

Inventor： Xia Li ,  Jianguo Yao ,  Bin Yang

IPC: G06N3/063 ,  G11C11/40 ,  G06F9/30 ,  G11C11/54 ,  G11C11/413 ,  H03K19/21

CPC classification number: G11C11/40 ,  G06F9/30029 ,  G06N3/063 ,  G11C11/413 ,  G11C11/54 ,  H03K19/215

Abstract: Certain aspects provide methods and apparatus for in-memory convolution computation. An example circuit for such computation generally includes a memory cell having a bit-line and a complementary bit-line and a computation circuit coupled to a computation input node of the circuit and at least one of the bit-line or the complementary bit-line. In certain aspects, the computation circuit comprises a counter, an NMOS transistor coupled to the memory cell, and a PMOS transistor coupled to the memory cell, drains of the NMOS and PMOS transistors being coupled to the counter.

公开(公告)号：US11437781B2

公开(公告)日：2022-09-06

申请号：US16803668

申请日：2020-02-27

Applicant: QUALCOMM Incorporated

Inventor： Gengming Tao ,  Bin Yang ,  Xia Li

IPC: H01S5/12 ,  H01S5/02 ,  H01S5/026 ,  H01S5/343 ,  H01S5/042 ,  H01S5/34

Abstract: A distributed feedback (DFB) laser that includes a substrate comprising a first surface and a second surface, wherein the substrate comprises silicon; a plurality of shallow trench isolations (STIs) located over the second surface of the substrate; a grating region located over the plurality of STIs and the substrate, wherein the grating region comprises a III-V semiconductor material; a non-intentional doping (NID) region located over the grating region; and a contact region located over the NID region.

公开(公告)号：US11201193B2

公开(公告)日：2021-12-14

申请号：US16752288

申请日：2020-01-24

Applicant: QUALCOMM Incorporated

Inventor： Bin Yang ,  Xia Li ,  Gengming Tao

IPC: H01L27/24 ,  H01L45/00

Abstract: Certain aspects of the present disclosure generally relate to a vertically stacked multilayer resistive random access memory (RRAM) and methods for fabricating such an RRAM. The vertically stacked multilayer RRAM generally includes a planar substrate layer and a plurality of metal-insulator-metal (MIM) stacks, each MIM stack structure of the plurality of MIM stacks comprising a plurality of MIM structures extending orthogonally above the planar substrate.

公开(公告)号：US20210351095A1

公开(公告)日：2021-11-11

申请号：US16868147

申请日：2020-05-06

Applicant: QUALCOMM Incorporated

Inventor： Gengming Tao ,  Bin Yang ,  Xia Li

IPC: H01L23/31 ,  H01L23/00 ,  H01L21/78 ,  H01L21/56

Abstract: Before a semiconductor die of a brittle compound semiconductor is encapsulated with a molding compound during package fabrication, side surfaces of the semiconductor die are treated to avoid or prevent surface imperfections from propagating and fracturing the crystal structure of the substrate of the III-V compound semiconductor under the stresses applied as the molding compound solidifies. Surfaces are treated to form a passivation layer, which may be a passivated layer of the substrate or a passivation material on the substrate. In a passivated layer, imperfections of an external layer are transformed to be less susceptible to fracture. Passivation material, such as a poly-crystalline layer on the substrate surface, diffuses stresses that are applied by the molding compound. Semiconductor dies in flip-chip and wire-bond chip packages with treated side surfaces as disclosed have a reduced incidence of failure caused by die fracturing.

公开(公告)号：US11139315B2

公开(公告)日：2021-10-05

申请号：US16669837

申请日：2019-10-31

Applicant: QUALCOMM Incorporated

Inventor： Xia Li ,  Haining Yang ,  Bin Yang

IPC: H01L27/11 ,  H01L29/51 ,  H01L29/78 ,  H01L27/1159 ,  H01L29/66 ,  H01L21/28

Abstract: Certain aspects of the present disclosure are directed to a semiconductor device. The semiconductor device generally includes a ferroelectric (FE) semiconductor device having a channel region; a gate oxide; a FE region, wherein the gate oxide is disposed between the FE region and the channel region; a gate region, wherein the FE region is disposed between the gate oxide and the gate region; a first semiconductor region disposed adjacent to the channel region; and a second semiconductor region disposed adjacent to the channel region. The semiconductor device may also include a transistor, wherein a region of the transistor is connected to the gate region, the first semiconductor region, or the second semiconductor region of the FE semiconductor device.

公开(公告)号：US10971615B2

公开(公告)日：2021-04-06

申请号：US16058388

申请日：2018-08-08

Applicant: QUALCOMM Incorporated

Inventor： Gengming Tao ,  Bin Yang ,  Xia Li

IPC: H01L29/15 ,  H01L29/778 ,  H01L29/06 ,  H01L29/66

Abstract: Certain aspects of the present disclosure provide a high electron mobility transistor (HEMT). The HEMT generally includes a gallium nitride (GaN) layer and an aluminum gallium nitride (AlGaN) layer disposed above the GaN layer. The HEMT also includes a source electrode, a gate electrode, and a drain electrode disposed above the AlGaN layer. The HEMT further includes n-doped protuberance(s) disposed above the AlGaN layer and disposed between at least one of: the gate electrode and the drain electrode; or the source electrode and the gate electrode. Each of the n-doped protuberances is separated from the gate electrode, the drain electrode, and the source electrode.

公开(公告)号：US10896981B1

公开(公告)日：2021-01-19

申请号：US16511093

申请日：2019-07-15

Applicant: QUALCOMM Incorporated

Inventor： Gengming Tao ,  Xia Li ,  Bin Yang

IPC: H01L29/93 ,  H01L29/66 ,  H01L29/778

Abstract: Aspects generally relate to a P-N junction varactor that can be integrated with high electron mobility transistor (HEMT) in a single device or die. The varactor and HEMT are fabricated with the same materials forming various layers of the varactor and HEMT. Using the same material stack-up to form the varactor and HEMT can reduce the number of processing steps during the fabrication of the integrated varactor and HEMT device. The integrated varactor and HEMT device may be used for RF circuits, such as radio frequency front end (RFFE) devices for use in 5G.

公开(公告)号：US10756206B2

公开(公告)日：2020-08-25

申请号：US15645188

申请日：2017-07-10

Applicant: QUALCOMM Incorporated

Inventor： Bin Yang ,  Xia Li ,  Gengming Tao ,  Periannan Chidambaram

IPC: H01L29/66 ,  H01L29/778 ,  H01L29/10 ,  H01L29/205 ,  H01L21/74 ,  H01L23/66 ,  H01L29/08 ,  H03F3/24 ,  H03F3/189 ,  H04W88/02

Abstract: A compound semiconductor field effect transistor may include a channel layer. The compound semiconductor transistor may also include a multi-layer epitaxial barrier layer on the channel layer. The channel layer may be on a doped buffer layer or on a first un-doped buffer layer. The compound semiconductor field effect transistor may further include a gate. The gate may be on a first tier of the multi-layer epitaxial barrier layer, and through a space between portions of a second tier of the multi-layer epitaxial barrier layer.

公开(公告)号：US10749017B1

公开(公告)日：2020-08-18

申请号：US16274094

申请日：2019-02-12

Applicant: QUALCOMM Incorporated

Inventor： Gengming Tao ,  Bin Yang ,  Xia Li

IPC: H01L29/737 ,  H01L29/08 ,  H01L29/205 ,  H01L29/40 ,  H01L29/66 ,  H01L29/10

Abstract: Power amplifiers in radio frequency circuits are typically implemented as heterojunction bipolar transistors. In applications such as in 5G systems, the circuits are expected to operate at very high speeds, e.g., up to 100 GHz. Also, a certain amount of output power should be maintained for stable operation. To achieve both high power and high speed, it is proposed to incorporate field plates in the heterojunction bipolar transistors to reduce electric field in the collector. This allows the breakdown voltage of the transistor to be high, which aids in power output. At the same time, the collector can be relatively thin, which aids in operation speed.

公开(公告)号：US10741702B2

公开(公告)日：2020-08-11

申请号：US16154021

申请日：2018-10-08

Applicant: QUALCOMM Incorporated

Inventor： Xia Li ,  Bin Yang ,  Kai Liu

IPC: H01L29/94 ,  H01L27/13 ,  H01L49/02 ,  H01L23/522 ,  H01L29/786 ,  H01L23/00 ,  H01L23/532

Abstract: Certain aspects of the present disclosure provide a variable transistor-based capacitive element implemented on a glass or dielectric substrate. Such a variable transistor-based capacitive element may be suitable for use as a tunable capacitor in a passive-on-glass (POG) device, for example. One example device having a tunable capacitance generally includes a glass or dielectric substrate and a transistor disposed above the glass or dielectric substrate. The transistor has a gate region, a drain region, and a source region, wherein a capacitance of the transistor is configured to vary based on a voltage between the gate region and the drain region.