知搜-全球专利检索

  1. Login
  2. Sign Up

Search Results

203 records (took 0.026 seconds)

    Multi-Tube Biofilter System for Treating Waste Gas
    114.
    发明申请
    Multi-Tube Biofilter System for Treating Waste Gas 有权
    用于处理废气的多管生物过滤系统

    公开(公告)号：US20130137170A1

    公开(公告)日：2013-05-30

    申请号：US13814240

    申请日：2011-07-27

    Applicant: Chunping Yang ,  Haining Yang ,  Hong Chen ,  Guanlong Yu ,  Guangming Zeng ,  Shenglian Luo

    Inventor： Chunping Yang ,  Haining Yang ,  Hong Chen ,  Guanlong Yu ,  Guangming Zeng ,  Shenglian Luo

    IPC: C12M1/12

    CPC classification number: C12M25/14 ,  B01D53/85 ,  B01D2257/708 ,  Y02A50/2359

    Abstract: Disclosed is a multi-tube biofilter system for treating waste gas. The multi-tube biofilter system includes a multi-tube biofilter and a nutrient solution supply system. The multi-tube biofilter includes an outer casing, at least two reticulated tubes disposed in the outer casing, a packing medium portion, and a nutrient solution spraying system. The outer casing is opened to define a gas inlet, a gas outlet, and a water outlet therein. The packing medium portion is attached to an outer surface of each of the reticulated tubes, wherein a liquid entering end of the nutrient solution spraying system is in communication with the nutrient solution supply system via a pipeline, and solution spraying ends of the nutrient solution spraying system face the reticulated tubes.

    Abstract translation: 公开了一种用于处理废气的多管生物滤池系统。 多管生物滤池系统包括多管生物过滤器和营养液供应系统。 多管生物过滤器包括外壳，设置在外壳中的至少两个网状管，填充介质部分和营养液喷洒系统。 外壳打开以在其中限定气体入口，气体出口和出水口。 包装介质部分附接到每个网状管的外表面，其中进入营养液喷射系统的一端的液体通过管道与营养液供应系统连通，并且喷洒营养液的溶液喷洒 系统面对网状管。

    Systems and methods for writing to multiple port memory circuits
    115.
    发明授权
    Systems and methods for writing to multiple port memory circuits 有权
    用于写入多个端口存储器电路的系统和方法

    公开(公告)号：US08194478B2

    公开(公告)日：2012-06-05

    申请号：US12699933

    申请日：2010-02-04

    Applicant: Haining Yang ,  Zhongze Wang ,  ChangHo Jung

    Inventor： Haining Yang ,  Zhongze Wang ,  ChangHo Jung

    IPC: G11C7/00

    CPC classification number: G11C8/16 ,  G11C11/412

    Abstract: A multiple-port RAM circuit has a data-in line coupled to multiple bit lines and multiple bit line bars. The circuit also has multiple word lines. A memory cell is coupled to the bit lines, bit line bars, and word lines. The circuit further includes a controller than enables the word lines to substantially simultaneously write a value from the bit lines to the memory cell.

    Abstract translation: 多端口RAM电路具有耦合到多个位线和多个位线条的数据输入线。 电路也有多条字线。 存储单元耦合到位线，位线条和字线。 电路还包括控制器，使得字线能够基本上同时从位线写入存储单元。

    Gate conductor structure
    116.
    发明授权
    Gate conductor structure 有权
    门导体结构

    公开(公告)号：US07943452B2

    公开(公告)日：2011-05-17

    申请号：US11609496

    申请日：2006-12-12

    Applicant: Wai-Kin Li ,  Haining Yang

    Inventor： Wai-Kin Li ,  Haining Yang

    IPC: H01L21/00 ,  H01L21/338 ,  H01L21/337 ,  H01L21/8238

    CPC classification number: H01L21/76841 ,  H01L21/823842 ,  H01L21/823871 ,  H01L22/12 ,  H01L23/58 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/78 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A gate conductor structure is provided having a barrier region between a N-type device and a P-type device, wherein the barrier region minimizes or eliminates cross-diffusion of dopant species across the barrier region. The barrier region comprises at least one sublithographic gap in the gate conductor structure. The sublithographic gap is formed by using self-assembling copolymers to form a sublithographic patterned mask over the gate conductor structure. According to one embodiment, at least one sublithographic gap is a slit or line that traverses the width of the gate conductor structure. The sublithographic gap is sufficiently deep to minimize or prevent cross-diffusion of the implanted dopant from the upper portion of the gate conductor. According to another embodiment, the sublithographic gaps are of sufficient density that cross-diffusion of dopants is reduced or eliminated during an activation anneal such that changes in Vt are minimized.

    Abstract translation: 提供了具有在N型器件和P型器件之间的势垒区域的栅极导体结构，其中所述势垒区域最小化或消除了所述阻挡区域上的掺杂剂物质的交叉扩散。 阻挡区域包括栅极导体结构中的至少一个亚光刻间隙。 通过使用自组装共聚物在栅极导体结构上形成亚光刻图案掩模来形成亚光刻间隙。 根据一个实施例，至少一个亚光刻间隙是穿过栅极导体结构的宽度的狭缝或线。 亚光刻间隙足够深以使注入的掺杂剂从栅极导体的上部最小化或防止交叉扩散。 根据另一个实施例，亚光刻间隙具有足够的密度，使得在激活退火期间掺杂剂的交叉扩散减少或消除，使得Vt的变化最小化。

    Device structures including backside contacts, and methods for forming same
    117.
    发明授权
    Device structures including backside contacts, and methods for forming same 有权
    包括背面触点的装置结构及其形成方法

    公开(公告)号：US07816231B2

    公开(公告)日：2010-10-19

    申请号：US11468068

    申请日：2006-08-29

    Applicant: Thomas W. Dyer ,  Haining Yang

    Inventor： Thomas W. Dyer ,  Haining Yang

    IPC: H01L21/3205 ,  H01L21/4763

    CPC classification number: H01L21/76898 ,  G03F9/7084 ,  H01L23/544 ,  H01L24/02 ,  H01L2223/54453 ,  H01L2924/01074 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043

    Abstract: The present invention relates to device structures having backside contacts that extend from a back surface of a substrate through the substrate to electrically contact frontside semiconductor devices. The substrate preferably further includes one or more alignment structures located therein, each of which is sufficiently visible at the back surface of the substrate. In this manner, backside lithographic alignment can be carried out using such alignment structures to form at least one back contact opening in a patterned resist layer over the back surface of the substrate. The formed back contact opening is lithographically aligned with the front semiconductor device and can be etched to form a back contact via that extends from the back surface of the substrate onto the front semiconductor device. Filling of the back contact via with a conductive material results in a conductive back contact that electrically contacts the front semiconductor device.

    Abstract translation: 本发明涉及具有从衬底的背表面延伸穿过衬底到背面半导体器件的背面接触的器件结构。 基板优选地还包括位于其中的一个或多个对准结构，其中每个在基板的背面处足够可见。 以这种方式，可以使用这种对准结构来进行背面光刻对准，以在衬底的背面上形成图案化抗蚀剂层中的至少一个后接触开口。 形成的后接触开口与前半导体器件光刻对准，并且可以被蚀刻以形成从衬底的背面延伸到前半导体器件上的后接触。 用导电材料填充背面接触孔导致与前半导体器件电接触的导电背接触。

    Structure and method for dual surface orientations for CMOS transistors
    118.
    发明授权
    Structure and method for dual surface orientations for CMOS transistors 失效
    用于CMOS晶体管的双面取向的结构和方法

    公开(公告)号：US07808082B2

    公开(公告)日：2010-10-05

    申请号：US11559571

    申请日：2006-11-14

    Applicant: Haining Yang ,  Thomas W. Dyer ,  Keith Kwong Hon Wong ,  Chih-Chao Yang

    Inventor： Haining Yang ,  Thomas W. Dyer ,  Keith Kwong Hon Wong ,  Chih-Chao Yang

    IPC: H01L21/335

    CPC classification number: H01L21/30608 ,  H01L21/02381 ,  H01L21/02433 ,  H01L21/02532 ,  H01L21/02609 ,  H01L21/02639 ,  H01L21/823821 ,  H01L27/11 ,  H01L27/1104 ,  H01L29/7853

    Abstract: The present invention provides structures and methods for providing facets with different crystallographic orientations than what a semiconductor substrate normally provides. By masking a portion of a semiconductor surface and exposing the rest to an anisotripic etch process that preferentially etches a set of crystallographic planes faster than others, new facets with different surface orientations than the substrate orientation are formed on the semiconductor substrate. Alternatively, selective epitaxy may be utilized to generate new facets. The facets thus formed are joined to form a lambda shaped profile in a cross-section. The electrical properties of the new facets, specifically, the enhanced carrier mobility, are utilized to enhance the performance of transistors. In a transistor with a channel on the facets that are joined to form a lambda shaped profile, the current flows in the direction of the ridge joining the facets avoiding any inflection in the direction of the current.

    Abstract translation: 本发明提供了提供具有不同于半导体衬底通常提供的不同晶体取向的刻面的结构和方法。 通过掩蔽半导体表面的一部分并将其余部分暴露于比其它晶体学优化蚀刻一组结晶平面的各向异性蚀刻工艺，在半导体衬底上形成具有不同于衬底取向的不同表面取向的新面。 或者，可以利用选择性外延生成新的面。 如此形成的小面被连接以在横截面中形成λ形轮廓。 新面的电特性，特别是增强的载流子迁移率被用于增强晶体管的性能。 在具有接合形成λ形轮廓的小平面上的通道的晶体管中，电流沿连接小面的脊的方向流动，避免了在电流方向上的任何拐点。

    Contact aperture and contact via with stepped sidewall and methods for fabrication thereof
    119.
    发明授权
    Contact aperture and contact via with stepped sidewall and methods for fabrication thereof 有权
    接触孔径和阶梯式侧壁接触孔及其制造方法

    公开(公告)号：US07687395B2

    公开(公告)日：2010-03-30

    申请号：US11555801

    申请日：2006-11-02

    Applicant: Haining Yang ,  Wai-Kin Li

    Inventor： Haining Yang ,  Wai-Kin Li

    IPC: H01L21/4763

    CPC classification number: H01L23/485 ,  H01L21/76897 ,  H01L21/823425 ,  H01L21/823475 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A semiconductor structure includes a semiconductor device including a contact region. The semiconductor structure also includes a passivation layer passivating the semiconductor device including the contact region. A narrow bottomed stepped sidewall contact aperture is located within the passivation layer to expose the contact region. A corresponding narrow bottomed stepped sidewall contact via is located within the narrow bottomed stepped sidewall contact aperture to contact the contact region. The narrow bottomed stepped sidewall contact aperture and contact via provide for improved contact to the contact region and reduced parasitic capacitance with respect to the semiconductor device. Methods for fabricating the narrow bottomed stepped sidewall contact aperture use a mask layer (either dimensionally diminished or dimensionally augmented) in conjunction with a two step etch method.

    Abstract translation: 半导体结构包括包括接触区域的半导体器件。 半导体结构还包括钝化层，钝化包括接触区域的半导体器件。 窄的有底阶梯式侧壁接触孔位于钝化层内以暴露接触区域。 相应的窄底部阶梯状侧壁接触通孔位于窄底部阶梯状侧壁接触孔内，以接触接触区域。 窄的有底阶梯式侧壁接触孔和接触通孔提供与接触区域的改善的接触并减小相对于半导体器件的寄生电容。 制造窄底阶阶侧壁接触孔的方法结合两步蚀刻方法使用掩模层（尺寸减小或尺寸增大）。

    Semiconductor device structures with reduced junction capacitance and drain induced barrier lowering and methods for fabricating such device structures and for fabricating a semiconductor-on-insulator substrate
    120.
    发明授权
    Semiconductor device structures with reduced junction capacitance and drain induced barrier lowering and methods for fabricating such device structures and for fabricating a semiconductor-on-insulator substrate 失效
    具有减小的结电容和漏极引起的屏障降低的半导体器件结构以及用于制造这种器件结构和用于制造绝缘体上半导体衬底的方法

    公开(公告)号：US07659178B2

    公开(公告)日：2010-02-09

    申请号：US11379655

    申请日：2006-04-21

    Applicant: Kangguo Cheng ,  Louis Lu-Chen Hsu ,  Jack Allan Mandelman ,  Haining Yang

    Inventor： Kangguo Cheng ,  Louis Lu-Chen Hsu ,  Jack Allan Mandelman ,  Haining Yang

    IPC: H01L21/311 ,  H01L21/3115

    CPC classification number: H01L29/66545 ,  H01L29/51 ,  H01L29/513 ,  H01L29/66636 ,  H01L29/66772 ,  H01L29/78603 ,  Y10S438/96

    Abstract: Semiconductor device structures with reduced junction capacitance and drain induced barrier lowering, methods for fabricating such device structures, and methods for forming a semiconductor-on-insulator substrate. The semiconductor structure comprises a semiconductor layer and a dielectric layer disposed between the semiconductor layer and the substrate. The dielectric layer includes a first dielectric region with a first dielectric constant and a second dielectric region with a second dielectric constant that is greater than the first dielectric constant. In one embodiment, the dielectric constant of the first dielectric region may be less than about 3.9 and the dielectric constant of the second dielectric region may be greater than about ten (10). The semiconductor-on-insulator substrate comprises a semiconductor layer separated from a bulk layer by an insulator layer of a high-dielectric constant material. The fabrication methods comprise modifying a region of the dielectric layer to have a lower dielectric constant.

    Abstract translation: 具有减小的结电容和漏极引发的屏障降低的半导体器件结构，用于制造这种器件结构的方法以及用于形成绝缘体上半导体衬底的方法。 半导体结构包括半导体层和设置在半导体层和衬底之间的电介质层。 电介质层包括具有第一介电常数的第一电介质区域和具有大于第一介电常数的第二介电常数的第二电介质区域。 在一个实施例中，第一电介质区域的介电常数可以小于约3.9，并且第二电介质区域的介电常数可以大于约十（10）。 绝缘体上半导体衬底包括通过高介电常数材料的绝缘体层与本体层分离的半导体层。 制造方法包括修改介电层的区域以具有较低的介电常数。

Patent Agency Ranking