公开(公告)号：US20020093078A1

公开(公告)日：2002-07-18

申请号：US10046995

申请日：2002-01-14

Inventor： Jong Sik Paek

IPC: H01L023/495

CPC classification number: H01L31/0203 ,  H01L2224/05573 ,  H01L2224/13025 ,  H01L2224/16237 ,  H01L2224/05624 ,  H01L2924/00014 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647

Abstract: An optical device package having improved conductor efficiency, optical coupling and thermal transfer, as well as various methods for packaging a semiconductor die provide reduced connection length, and improved optical and thermal characteristics. In one package, a conductive circuit pattern disposed on a transparent or translucent cover connects bond pads on the light receiving surface of the semiconductor die to external electrical contacts. The construction of the package reduces connection length and eliminates the air gap between the glass and the die. In another package, a substrate having a protruding wall supports the glass and the substrate provides an electrical connection to terminals for connection to an external device. In another package, the glass is supported by a die mounting board that supports the semiconductor die and includes leads for connection to an external device. In other packages, the glass is supported directly by the semiconductor die and the die is supported by an encapsulated assembly including leads that support the semiconductor die.

Abstract translation: 具有改进的导体效率，光学耦合和热传递的光学器件封装以及用于封装半导体管芯的各种方法提供了缩短的连接长度，以及改进的光学和热特性。 在一个封装中，布置在透明或半透明盖上的导电电路图形将半导体管芯的光接收表面上的接合焊盘连接到外部电触头。 封装的结构减少了连接长度，并消除了玻璃和模具之间的气隙。 在另一个封装中，具有突出壁的基板支撑玻璃，并且基板提供与用于连接到外部装置的端子的电连接。 在另一个封装中，玻璃由支撑半导体管芯的管芯安装板支撑，并且包括用于连接到外部设备的引线。 在其他封装中，玻璃直接由半导体管芯支撑，并且管芯由包括支撑半导体管芯的引线的封装组件支撑。

公开(公告)号：US20020086500A1

公开(公告)日：2002-07-04

申请号：US09932053

申请日：2001-08-18

Applicant: Siliconware Precision Industries, Co., Ltd.

Inventor： Chi Chuan Wu ,  Chian Ping Huang ,  Jui-Yu Chuang ,  Ho-Yi Tsai ,  Yude Chu

IPC: H01L021/30 ,  H01L023/495 ,  H01L021/46 ,  H01L023/28 ,  H01L021/48 ,  H01L021/50 ,  H01L021/44 ,  H01L023/48 ,  H01L023/52

CPC classification number: H01L24/32 ,  H01L23/3128 ,  H01L23/642 ,  H01L24/29 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/83 ,  H01L2224/2919 ,  H01L2224/32057 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2224/83136 ,  H01L2224/83192 ,  H01L2224/83385 ,  H01L2224/8385 ,  H01L2224/92 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/07802 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19103 ,  H01L2924/19105 ,  H01L2924/00 ,  H01L2924/00015 ,  H01L2224/05599 ,  H01L2924/00012

Abstract: A semiconductor package and its fabricating method are proposed, in which a plurality of passive devices are integrated under a semiconductor chip, so as to increase the layout number of the passive devices in the semiconductor package and enhance the flexibility of substrate routability, as well as reduce an occupied area of a substrate for miniaturize the semiconductor package in profile. Moreover, as the integrated passive devices are further encapsulated by using an insulative material prior to a molding process, the dislocation of the passive devices caused by a high temperature and mold flow of a molding resin can be prevented from occurrence during molding. Furthermore, the encapsulated passive devices are prevented from contacting bonding wires, allowing the occurrence of short circuit to be avoided and quality of the packaged product to be assured.

Abstract translation: 提出了一种半导体封装及其制造方法，其中多个无源器件集成在半导体芯片之下，以便增加半导体封装中的无源器件的布局数量并提高衬底可路由性的灵活性，以及 减少基板的占用面积，以使半导体封装的形状小型化。 此外，由于通过在模制工艺之前使用绝缘材料进一步封装集成的无源器件，因此可以防止在模制期间由模制树脂的高温和模具流引起的无源器件的位错。 此外，防止封装的无源器件接触接合线，从而避免短路的发生，并确保封装产品的质量。

公开(公告)号：US20020084515A1

公开(公告)日：2002-07-04

申请号：US09986341

申请日：2001-11-08

Inventor： Richard W. Arnold ,  Weldon Beardain ,  Daniel W. Prevedel ,  Donald E. Riley ,  Lester L. Wilson

IPC: H01L023/495

CPC classification number: G01R1/0483 ,  H01L24/48 ,  H01L24/49 ,  H01L25/0657 ,  H01L2224/05554 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/4847 ,  H01L2224/49109 ,  H01L2225/0651 ,  H01L2225/06527 ,  H01L2225/06572 ,  H01L2225/06582 ,  H01L2225/06596 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/16195 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599

Abstract: An apparatus for testing a semiconductor die and the method wherein there is provided a package having a cavity therein with a plurality of terminals in the package disposed at the periphery of the cavity. A semiconductor die to be tested and having a plurality of bond pads thereon is disposed in the cavity and an interconnecting layer having electrically conductive paths thereon is also disposed in the cavity, each of the paths having first and second spaced apart regions thereon, the first region of each path being aligned with and contacting a bond pad. An interconnection is provided between the second spaced apart region of each of the paths and one of the plurality of terminals. The second spaced apart region of each of the paths is preferably a bump aligned with and contacting one of the plurality of terminals. A compliant layer is preferably disposed over the interconnecting layer and provides a force causing engagement of at least the first spaced apart regions and the bond pads. The first region is preferably a compliant bump probe tip having a first predetermined height above the layer and includes a standoff on the layer having a second predetermined height above the layer less than the first height.

Abstract translation: 一种用于测试半导体管芯的设备及其方法，其中提供了一种其中具有空腔的封装，该封装中的多个端子设置在空腔周边。 待测试并且在其上具有多个接合焊盘的半导体管芯设置在空腔中，并且其上具有导电路径的互连层也设置在空腔中，每个路径上具有第一和第二间隔开的区域，第一 每个路径的区域与接合焊盘对准并接触。 在每个路径的第二间隔开的区域和多个端子中的一个之间提供互连。 每个路径的第二间隔开的区域优选地是与多个端子之一对准并接触多个端子之一的凸块。 优选地，柔性层设置在互连层上方并且提供导致至少第一间隔开的区域和接合焊盘的接合的力。 第一区域优选地是具有在层上方的第一预定高度的柔顺凸起探针尖端，并且包括在该层上方的具有小于第一高度的第二预定高度的间隔。

公开(公告)号：US20020075663A1

公开(公告)日：2002-06-20

申请号：US09973317

申请日：2001-10-09

Inventor： Gunter Aflenzer ,  Joachim Heinz Schober ,  Marcus Toth

IPC: H01L023/495 ,  H05K007/02

CPC classification number: G06K19/077 ,  G06K19/07745 ,  G06K19/07749 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2924/00014

Abstract: A module (1) for contactless communication includes a plurality of electrical components (4, 5, 6, 7, 8) which each have at least two contact faces (9, 10, 11, 12, 13, 14, 15, 16) for the electrical connection. The electrical components (4, 5, 6, 7, 8) of the module are mounted both on a component side (MB) and an on adhesive side (MK) of a lead frame (M) formed by metal strips (MS). During the manufacture of the module (1) the metal strips (MS) of the lead frame (M) are held in one plane (E) and in position by means of an adhesive tape (K). The adhesive tape (K) has openings (A1, A2, A3, A4, A5, A6) at given positions of the lead frame (M) so as to enable electrical components to be mounted on the adhesive side (MK) of the lead frame (M).

Abstract translation: 用于非接触式通信的模块（1）包括多个电气部件（4,5,6,7,8），每个电气部件具有至少两个接触面（9,10,11,12,13,14,15,16） 用于电气连接。 模块的电气部件（4,5,6,7,8）都安装在由金属条（MS）形成的引线框架（M）的部件侧（MB）和粘合剂侧（MK）上。 在模块（1）的制造期间，引线框架（M）的金属条（MS）通过粘合带（K）保持在一个平面（E）中并在适当位置。 粘合带（K）在引线框架（M）的给定位置处具有开口（A1，A2，A3，A4，A5，A6），以使电气部件能够安装在引线的粘合剂侧（MK）上 框架（M）。

公开(公告)号：US20020074648A1

公开(公告)日：2002-06-20

申请号：US10077451

申请日：2002-02-14

Inventor： Richard W. Wensel

IPC: H01L023/495

CPC classification number: H01L21/565 ,  H01L23/4334 ,  H01L24/48 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2924/00014 ,  H01L2924/0102 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2224/85399 ,  H01L2924/00012

Abstract: A semiconductor device includes a heat sink adjacent to a die. A dam is positioned at the peripheral edges of the heat sink. During a transfer molding process, the dam serves two purposes. First, the dam prevents damage to the mold. Second, the dam prevents encapsulant packaging compound material from flowing onto the heat sink. The dam may be a gasket. The dam may also be a burr created by, for example, stamping the bottom of the heat sink. The dam may include copper, polyamides, and leadlock tape. The dam may be permanently connected to the heat sink for removal following packaging. The dam may be removed mechanically, through the use of heat, or during an electrolytic deflash cycle.

Abstract translation: 半导体器件包括与模具相邻的散热器。 大坝位于散热器的周边边缘。 在传递模塑过程中，大坝有两个目的。 首先，防止大坝损坏模具。 第二，防止密封剂包装复合材料流入散热片。 大坝可能是垫圈。 大坝也可能是由例如冲压散热器底部而产生的毛刺。 大坝可以包括铜，聚酰胺和铅锁胶带。 大坝可以永久连接到散热器，以便包装后取出。 大坝可以通过机械方式，通过使用热量，或者在电解消除循环过程中被去除。

公开(公告)号：US20020074639A1

公开(公告)日：2002-06-20

申请号：US09995322

申请日：2001-11-26

Applicant: Samsung Electronics, Co. Ltd.

Inventor： Min-Ha Kim ,  Joong-Hyun Baek

IPC: H01L023/495

CPC classification number: H01L23/3677 ,  H01L25/0652 ,  H01L2224/16 ,  H01L2924/00014 ,  H01L2924/16152 ,  H01L2224/0401

Abstract: Provided is a semiconductor memory module including semiconductor devices using solder balls as outer connection terminals, which reduces the deterioration of solder joint reliability (SJR) due to the difference in the thermal expansion coefficients of the module components. The memory module includes a module board, an upper heat sink, a lower heat sink and a linking means. The linking means is formed to have a structure that makes it possible to absorb contraction and expansion within the semiconductor module due to the different thermal expansion coefficients of the upper heat sink, the lower heat sink and the module board.

Abstract translation: 提供了一种半导体存储器模块，其包括使用焊球作为外部连接端子的半导体器件，由于模块部件的热膨胀系数的差异，可以降低焊点可靠性（SJR）的劣化。 存储器模块包括模块板，上部散热器，下部散热器和连接装置。 连接装置形成为具有能够吸收上部散热器，下部散热器和模块基板的热膨胀系数不同而吸收半导体模块内的收缩膨胀的结构。

公开(公告)号：US20020074630A1

公开(公告)日：2002-06-20

申请号：US10076580

申请日：2002-02-19

Applicant: FUJITSU LIMITED

Inventor： Fumihiko Ando ,  Akira Takashima ,  Hiroshi Onodera ,  Eiji Yoshida ,  Kazuo Teshirogi

IPC: H01L023/495

CPC classification number: H01L25/50 ,  H01L23/49816 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/05001 ,  H01L2224/05023 ,  H01L2224/05548 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2225/06541 ,  H01L2225/06555 ,  H01L2225/06582 ,  H01L2225/06586 ,  H01L2225/06593 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/12042 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A plurality of semiconductor devices can be mounted on a mounting board in a three-dimensional structure by stacking one on another with a simple structure. A semiconductor element is mounted on a first surface of an interposer. Electrode pads connected to the semiconductor element are arranged around the semiconductor element on the first surface of the interposer. Protruding electrodes are provided on the respective electrode pads. Through holes are formed in the interposer so as to extend from a second surface opposite to the first surface of the redistribution substrate to the respective electrode pads. The semiconductor element is encapsulated by a seal resin. Each of the protruding electrodes is higher than the sealed portion of the semiconductor element.

公开(公告)号：US20020074629A1

公开(公告)日：2002-06-20

申请号：US10071943

申请日：2002-02-05

Inventor： David J. Corisis ,  Brent Keeth

IPC: H01L023/495

CPC classification number: H01L23/66 ,  H01L23/645 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/48247 ,  H01L2224/49111 ,  H01L2224/49171 ,  H01L2924/00014 ,  H01L2924/01023 ,  H01L2924/01047 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599

Abstract: Devices and methods for reducing lead inductance in integrated circuit (IC) packages. More specifically to an integrated circuit package configuration for high speed applications where the inductance of the leads is reduced or minimized in high capacity semiconductor device packages. The integrated circuit package assembly comprises a substrate, semiconductor device, insulating covering or coating, if desired, a semiconductor device retainer, lead frame, and wire bond interconnections.

公开(公告)号：US20020072212A1

公开(公告)日：2002-06-13

申请号：US09957120

申请日：2001-09-20

Inventor： David Light

IPC: H01L021/44 ,  H01L021/48 ,  H01L021/50 ,  H01L021/4763 ,  H01L023/495 ,  H01L023/48 ,  H01L023/52

CPC classification number: H01L24/81 ,  H01L21/6835 ,  H01L23/49811 ,  H01L24/97 ,  H01L29/0657 ,  H01L2224/81801 ,  H01L2224/97 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2224/81

Abstract: Leads are connected between first and second elements so that a first end of each lead is connected to the first element and a second end of each lead is connected to the second element. and the elements are moved away from one another so as to bend the leads towards a vertically-extensive disposition. The direction of each lead, prior to the movement step, is represented by a lead direction vector from the first end of the lead to the second end of the same lead. At least some of these lead direction vectors are non-parallel with at least some other lead direction vectors, but the various lead direction vectors have components in a common direction. During the vertical movement step, the first element is moved in a horizontal direction of motion in this common direction, thereby moving the first end of each lead horizontally toward the second end of that lead, so as to provide or maintain slack in the leads.

Abstract translation: 引线连接在第一和第二元件之间，使得每个引线的第一端连接到第一元件，并且每个引线的第二端连接到第二元件。 并且元件彼此远离地移动，以便将引线弯曲成垂直方向的布置。 在移动步骤之前的每个引线的方向由从引线的第一端到同一引线的第二端的引导方向矢量表示。 这些引导方向向量中的至少一些与至少一些其它引导方向向量不平行，但是各种引导方向向量在共同方向上具有分量。 在垂直移动步骤期间，第一元件沿着该公共方向在水平运动方向上移动，从而使每个引线的第一端水平地朝向引线的第二端移动，以便在引线中提供或保持松弛。

公开(公告)号：US20020060356A1

公开(公告)日：2002-05-23

申请号：US09845272

申请日：2001-05-01

Applicant: MITSUBISHI DENKI KABUSHIKI KAISHA

Inventor： Hiroshi Nishibori ,  Masakazu Fukada ,  Takanobu Yoshida ,  Naoki Yoshimatsu ,  Haruo Takao ,  Nobuyoshi Kimoto ,  Yasumi Uegai

IPC: H01L023/495

CPC classification number: H05K3/0061 ,  C04B37/026 ,  C04B2237/121 ,  C04B2237/122 ,  C04B2237/123 ,  C04B2237/343 ,  C04B2237/366 ,  C04B2237/402 ,  C04B2237/407 ,  C04B2237/704 ,  C04B2237/706 ,  C04B2237/708 ,  C04B2237/72 ,  C04B2237/86 ,  H01L23/049 ,  H01L23/3735 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/32225 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/48137 ,  H01L2224/73265 ,  H01L2924/01078 ,  H01L2924/13091 ,  H01L2924/1532 ,  H01L2924/16195 ,  H01L2924/19107 ,  H05K1/0306 ,  H05K1/09 ,  H05K3/341 ,  H05K2201/2036 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/20755 ,  H01L2924/20756 ,  H01L2924/20757 ,  H01L2924/20758 ,  H01L2924/20759 ,  H01L2924/2075 ,  H01L2924/2076 ,  H01L2924/20754

Abstract: It is an object to provide a power semiconductor device having a circuit pattern and a lower pattern made of an Al alloy for cost reduction and enabling reduction in heat resistance and improvement in resistance of a soldering layer to heat cycle. A substrate of semiconductor elements is mounted on a metal base plate made of a Cu alloy. The substrate of semiconductor elements includes an insulating substrate made of ceramics or the like. The circuit pattern and the lower pattern both made of an Al alloy are formed on an upper surface and a lower surface of the insulating substrate. The lower pattern is provided on an entire surface of the insulating substrate and joined onto the metal base plate through the soldering layer. Thicknesses of the metal base plate and the insulating substrate are respectively set to be 3.5 to 5.5 mm and 0.5 to 1 mm, for example. A thickness of the circuit pattern is set to be 0.4 to 0.6 mm and thicknesses of the lower pattern and the soldering layer are respectively set to be 0.2 mm or less and 100 to 300 nullm.

Abstract translation: 本发明的目的是提供一种功率半导体器件，其具有电路图案和由Al合金制成的下部图案，用于降低成本，并且能够降低耐热性并提高焊接层对热循环的电阻。 将半导体元件的基板安装在由Cu合金制成的金属基板上。 半导体元件的基板包括由陶瓷等制成的绝缘基板。 由Al合金制成的电路图形和下部图案形成在绝缘基板的上表面和下表面上。 下部图案设置在绝缘基板的整个表面上，并通过焊接层接合到金属基板上。 金属基板和绝缘基板的厚度例如分别设定为3.5〜5.5mm，0.5〜1mm。 电路图案的厚度设定为0.4〜0.6mm，下图案和焊接层的厚度分别设定为0.2mm以下，100〜300μm。