公开(公告)号：US20230317520A1

公开(公告)日：2023-10-05

申请号：US17712461

申请日：2022-04-04

Applicant: Winbond Electronics Corp.

Inventor： Chun-Hung LIN ,  Kao-Tsair TSAI ,  Chung-Hsien LIU ,  Tz-Hau GUO ,  Yen-Jui CHU

IPC: H01L21/768 ,  H01L21/8234

CPC classification number: H01L21/76897 ,  H01L21/76816 ,  H01L21/823475 ,  H01L21/76834

Abstract: A manufacturing method for a semiconductor structure is provided. First active areas, a second active area, and a third active area are formed. A first dielectric layer is formed on the active areas. A patterned region that includes a cavity region and a dielectric region is formed in the first dielectric layer, and the cavity region surrounds the dielectric region. A filling layer is formed in the cavity region. Multiple first contact holes and at least one second contact hole that penetrate the first dielectric layer are formed. Each first contact hole exposes a portion of the corresponding first active area, and the second contact hole replaces the dielectric region and exposes a portion of the second active area. Metal layers are filled in to the first contact holes and the second contact hole.

公开(公告)号：US11776910B2

公开(公告)日：2023-10-03

申请号：US17313558

申请日：2021-05-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tsung-Ling Tsai ,  Shen-Nan Lee ,  Mrunal A. Khaderbad ,  Chung-Wei Hsu ,  Chen-Hao Wu ,  Teng-Chun Tsai

IPC: H01L23/535 ,  H01L23/528 ,  H01L23/522 ,  H01L23/532 ,  H01L21/768

CPC classification number: H01L23/535 ,  H01L21/7684 ,  H01L21/76805 ,  H01L21/76816 ,  H01L21/76847 ,  H01L21/76879 ,  H01L21/76895 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/53209 ,  H01L23/53252 ,  H01L23/53266

Abstract: Partial barrier-free vias and methods for forming such are disclosed herein. An exemplary interconnect structure of a multilayer interconnect feature includes a dielectric layer. A cobalt-comprising interconnect feature and a partial barrier-free via are disposed in the dielectric layer. The partial barrier-free via includes a first via plug portion disposed on and physically contacting the cobalt-comprising interconnect feature and the dielectric layer, a second via plug portion disposed over the first via plug portion, and a via barrier layer disposed between the second via plug portion and the first via plug portion. The via barrier layer is further disposed between the second via plug portion and the dielectric layer. The cobalt-comprising interconnect feature can be a device-level contact or a conductive line of the multilayer interconnect feature. The first via plug portion and the second via plug portion can include tungsten, cobalt, and/or ruthenium.

公开(公告)号：US11776813B2

公开(公告)日：2023-10-03

申请号：US17511042

申请日：2021-10-26

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Cheng-Hsiang Fan

IPC: H01L21/033 ,  H01L21/308 ,  H01L21/762 ,  H01L21/768 ,  H01L21/764 ,  H01L21/311

CPC classification number: H01L21/0337 ,  H01L21/308 ,  H01L21/31144 ,  H01L21/764 ,  H01L21/7682 ,  H01L21/76229 ,  H01L21/76816 ,  H01L21/76885 ,  H01L2221/1036

Abstract: The present disclosure provides a method for preparing a semiconductor device structure with fine patterns at different levels. The method includes forming a hard mask material over a substrate; etching the hardmask material to form hard mask pillars; forming spacers over sidewall surfaces of the hard mask pillars; etching the hard mask pillars and the target material by using the spacers as a mask to integrally forming a plurality of target structures, a high-level recesses in one of the plurality of target structures and a low-level recess between two target structures; and integrally forming a high-level conductive pattern in the high-level conductive pattern and a low-level conductive pattern in the low-level recess.

公开(公告)号：US20230307350A1

公开(公告)日：2023-09-28

申请号：US17701509

申请日：2022-03-22

Applicant: Micron Technology, Inc.

Inventor： Lifang Xu ,  Indra V. Chary ,  Richard J. Hill

IPC: H01L23/522 ,  H01L23/528 ,  H01L23/535 ,  H01L21/768

CPC classification number: H01L23/5221 ,  H01L23/5283 ,  H01L23/535 ,  H01L21/76816 ,  H01L21/76895

Abstract: A microelectronic device includes a stack structure having blocks separated by dielectric slot structures and each including a vertically alternating sequence of conductive structures and insulative structures arranged in tiers. At least one of the blocks includes an upper stadium structure, two crest regions, a lower stadium structure, and two bridge regions. The upper stadium structure extends from and between two of the dielectric slot structures, and includes staircase structures having steps including edges of some of the tiers. The two crest regions are horizontally offset from the upper stadium structure. The lower stadium structure is below the upper stadium structure, is interposed between the two crest regions, and includes additional staircase structures. The two bridge regions are interposed between the lower stadium structure and the two of the dielectric slot structures, and extend between the two crest regions. Related memory devices, electronic systems, and methods are also described.

公开(公告)号：US11769672B2

公开(公告)日：2023-09-26

申请号：US17218886

申请日：2021-03-31

Applicant: Semiconductor Manufacturing International (Shanghai) Corporation ,  Semiconductor Manufacturing International (Beijing) Corporation

Inventor： Jisong Jin

IPC: H01L21/311 ,  H01L21/768 ,  H01L21/3115

CPC classification number: H01L21/31144 ,  H01L21/76816 ,  H01L21/31155

Abstract: A semiconductor structure and a forming method thereof are provided. In one form, a forming method includes: forming separated mandrel lines, where opposite sidewalls of adjacent mandrel lines in a second direction are a first sidewall and a second sidewall; forming a sacrificial spacer on a sidewall of the mandrel line; forming a sacrificial layer on a part of the base between adjacent sacrificial spacers; forming a filling layer on the base; removing the sacrificial layer to form an opening; removing the sacrificial spacer to form a trench; forming a mask spacer on a sidewall of the trench, where the mask spacer is further filled between the sidewall of the mandrel line and the filling layer, and the mask spacer located on the sidewall of the trench forms a first groove; forming a second groove running through the filling layer between the sidewall of the trench and the mask spacer located on the second sidewall; removing the mandrel line to form a third groove, where a cutting layer is formed in at least one of the third groove, the second groove, and the first groove, and the cutting layer cuts the corresponding groove along the first direction; and patterning a target layer below the third groove, the second groove, and the first groove to form a target pattern. The embodiments in the present disclosure improve the pattern precision of the target pattern.

公开(公告)号：US20230290676A1

公开(公告)日：2023-09-14

申请号：US17989438

申请日：2022-11-17

Applicant: Tokyo Electron Limited

Inventor： David Power ,  David Conklin ,  Jodi Grzeskowiak ,  Michael Murphy

IPC: H01L21/768 ,  H01L21/033 ,  H01L21/311

CPC classification number: H01L21/76816 ,  H01L21/0337 ,  H01L21/31144 ,  H01L21/76897

Abstract: A method of patterning a substrate, where the method includes: forming first structures over a memorization layer, the first structures including a first row of lines that are parallel with each other and spaced apart from each other; executing a first anti-spacer formation process to form first trenches along sidewalls of the first structures and sidewalls of a first fill material, the first trenches defining a first etch pattern; transferring the first etch pattern into the memorization layer and removing materials above the memorization layer; forming second structures over the memorization layer, the second structures including a second row of lines that are parallel with each other and spaced apart, placement of the second row of lines being shifted relative to the first row of lines; executing a second anti-spacer formation process to form second trenches formed along sidewalls of the second structures and sidewalls of a second fill material, the second trenches defining a second etch pattern; and transferring the second etch pattern into the memorization layer and removing materials above the memorization layer.

公开(公告)号：US11742288B2

公开(公告)日：2023-08-29

申请号：US17242224

申请日：2021-04-27

Applicant: SK hynix Inc.

Inventor： Sang Hyun Sung ,  Sung Lae Oh

IPC: H01L23/528 ,  H01L23/522 ,  H01L21/768 ,  H10B41/27 ,  H10B43/27

CPC classification number: H01L23/5283 ,  H01L21/76816 ,  H01L21/76877 ,  H01L23/5226 ,  H10B41/27 ,  H10B43/27

Abstract: A three-dimensional memory device includes a plurality of electrode stacks stacked on a substrate in a vertical direction, each of the plurality of electrode stacks including a plurality of interlayer dielectric layers alternately stacked in the vertical direction with a plurality of electrode layers; and a plurality of staircase structures defined in the plurality of electrode stacks, each of the plurality of staircase structures configured by pad regions of electrode layers in an electrode stack that are disposed in a staircase shape, a staircase structure of an electrode stack lower in the plurality of electrode stacks has a larger width than a staircase structure of an electrode stack that is higher in the plurality of electrode stacks.

公开(公告)号：US11742286B2

公开(公告)日：2023-08-29

申请号：US17345871

申请日：2021-06-11

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Chia-Hsiang Hsu

IPC: H01L23/528 ,  H01L23/535 ,  H01L21/768 ,  H01L23/532 ,  H01L23/00

CPC classification number: H01L23/528 ,  H01L21/7682 ,  H01L21/76895 ,  H01L23/535 ,  H01L23/5329 ,  H01L21/76816 ,  H01L24/33

Abstract: The present disclosure provides a semiconductor device with an interconnect part and a method for forming the semiconductor device. The semiconductor device includes a first source/drain structure disposed over a carrier substrate, and a backside contact disposed over and electrically connected to the first source/drain structure. The semiconductor device also includes an interconnect part disposed over the backside contact. The interconnect part includes a lower redistribution layer electrically connected to the backside contact, and an upper redistribution layer disposed over the lower redistribution layer. The interconnect part also includes an interconnect frame disposed between and electrically connected to the lower redistribution layer and the upper redistribution layer. The interconnect part further includes a passivation structure surrounding the interconnect frame.

公开(公告)号：US20230262966A1

公开(公告)日：2023-08-17

申请号：US17719343

申请日：2022-04-12

Applicant: Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： YAOGUANG XU ,  Chien-Cheng Tsai ,  JUNYI ZHENG ,  JIANSHAN WU ,  ZHIYI ZHOU

IPC: H01L27/108 ,  H01L21/768 ,  H01L23/528

CPC classification number: H01L27/10897 ,  H01L27/10894 ,  H01L21/76816 ,  H01L23/528

Abstract: A semiconductor structure includes an array of active patterns, a peripheral pattern around the array of active patterns, and at least a branch pattern connected to an inner edge of the peripheral pattern. The active patterns respectively extend along a first direction and are arranged end-to-end along the first direction and side-by-side along a second direction that is different form the first direction. The branch pattern extends along the first direction. An end portion of the branch pattern and an end portion of one of the active patterns that is immediately side-by-side next to the branch pattern are flush along the second direction.

公开(公告)号：US20230261109A1

公开(公告)日：2023-08-17

申请号：US18302452

申请日：2023-04-18

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Lin-Yu HUANG ,  Jia-Chuan YOU ,  Chia-Hao CHANG ,  Tien-Lu LIN ,  Yu-Ming LIN ,  Chih-Hao WANG

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/308 ,  H01L21/768

CPC classification number: H01L29/785 ,  H01L29/66795 ,  H01L21/3086 ,  H01L21/76877 ,  H01L21/3081 ,  H01L21/76816

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a contact over a source/drain region of a fin structure, a gate stack over a channel region of the fin structure, a first mask layer covering the gate stack, and a second mask layer covering the contact. A side surface of the first mask layer is direct contact with a side surface of the second mask layer, and the first mask layer includes a portion directly below the second mask layer.