公开(公告)号：US12051466B2

公开(公告)日：2024-07-30

申请号：US18301745

申请日：2023-04-17

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Yu-Der Chih ,  Jonathan Tsung-Yung Chang ,  Yun-Sheng Chen ,  Maybe Chen ,  Ya-chin King ,  Wen Zhang Lin ,  Chrong Jung Lin ,  Hsin-Yuan Yu

IPC: G11C11/00 ,  G11C13/00 ,  H10B63/00 ,  H10N70/20

CPC classification number: G11C13/004 ,  G11C13/0069 ,  H10B63/30 ,  H10N70/253 ,  G11C2013/0045 ,  G11C2013/0078

Abstract: Disclosed herein are related to a memory cell including one or more programmable resistors and a control transistor. In one aspect, a programmable resistor includes a gate structure and one or more source/drain structures for forming a transistor. A resistance of the programmable resistor may be set by applying a voltage to the gate structure, while the control transistor is enabled. Data stored by the programmable resistor can be read by sensing current through the programmable resistor, while the control transistor is disabled. In one aspect, the one or more programmable resistors and the control transistor are implemented by same type of components, allowing the memory cell to be formed in a compact manner through a simplified the fabrication process.

公开(公告)号：US12027205B2

公开(公告)日：2024-07-02

申请号：US17828979

申请日：2022-05-31

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Zheng-Jun Lin ,  Chung-Cheng Chou ,  Yu-Der Chih

IPC: G11C13/00

CPC classification number: G11C13/0069 ,  G11C13/0026 ,  G11C13/0033 ,  G11C2213/79

Abstract: A memory device includes RRAM memory cells configured to form a zero-transistor and one-resistor (0T1R) array structure in which access transistors of the RRAM memory cells are bypassed or removed. Alternatively, the access transistors of the RRAM memory cells may be arranged in a parallel structure to reduce associated IR drop and thus enable reduced write voltage operation.

公开(公告)号：US11915752B2

公开(公告)日：2024-02-27

申请号：US17709662

申请日：2022-03-31

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Yu-Der Chih ,  Chung-Cheng Chou ,  Chun-Yun Wu ,  Chen-Ming Hung

IPC: G11C13/00

CPC classification number: G11C13/0069 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/0038 ,  G11C13/004 ,  G11C13/0064

Abstract: A memory device includes a main array comprising main memory cells; a redundancy array comprising redundancy memory cells; and write circuitry configured to perform a first programming operation on a main memory cell, to detect whether a current of the main memory cell exceeds a predefined current threshold during the first programming operation, and to disable a second programming operation for a redundancy memory cell if the current of the main memory cell exceeds the predefined current threshold during the first programming operation.

公开(公告)号：US20240029791A1

公开(公告)日：2024-01-25

申请号：US18352127

申请日：2023-07-13

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Hiroki Noguchi ,  Yu-Der Chih ,  Yih Wang

IPC: G11C13/00 ,  G11C11/22 ,  G11C11/16

CPC classification number: G11C13/0069 ,  G11C11/2275 ,  G11C11/1675 ,  G11C2013/0092

Abstract: A memory device includes: a memory cell array comprising a plurality of memory cells; a temperature sensor configured to detect a temperature of the memory cell array; a write circuit configured to write data into the plurality of memory cells; and a controller coupled to the temperature sensor and the write circuit, wherein the controller is configured to determine a target write pulse width used by the write circuit based on the detected temperature of the memory device.

公开(公告)号：US20230207005A1

公开(公告)日：2023-06-29

申请号：US17828979

申请日：2022-05-31

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Zheng-Jun Lin ,  Chung-Cheng Chou ,  Yu-Der Chih

IPC: G11C13/00

CPC classification number: G11C13/0069 ,  G11C13/0026 ,  G11C13/0033 ,  G11C2213/79

Abstract: A memory device includes RRAM memory cells configured to form a zero-transistor and one-resistor (0T1R) array structure in which access transistors of the RRAM memory cells are bypassed or removed. Alternatively, the access transistors of the RRAM memory cells may be arranged in a parallel structure to reduce associated IR drop and thus enable reduced write voltage operation.

公开(公告)号：US11646079B2

公开(公告)日：2023-05-09

申请号：US17337781

申请日：2021-06-03

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Yu-Der Chih ,  Maybe Chen ,  Yun-Sheng Chen ,  Wen Zhang Lin ,  Jonathan Tsung-Yung Chang ,  Chrong Jung Lin ,  Ya-Chin King ,  Hsin-Yuan Yu

IPC: G11C11/00 ,  G11C13/00 ,  H01L45/00 ,  H01L27/24

CPC classification number: G11C13/004 ,  G11C13/0069 ,  H01L27/2436 ,  H01L45/1206 ,  G11C2013/0045 ,  G11C2013/0078

Abstract: Disclosed herein are related to a memory cell including one or more programmable resistors and a control transistor. In one aspect, a programmable resistor includes a gate structure and one or more source/drain structures for forming a transistor. A resistance of the programmable resistor may be set by applying a voltage to the gate structure, while the control transistor is enabled. Data stored by the programmable resistor can be read by sensing current through the programmable resistor, while the control transistor is disabled. In one aspect, the one or more programmable resistors and the control transistor are implemented by same type of components, allowing the memory cell to be formed in a compact manner through a simplified the fabrication process.

公开(公告)号：US20220406386A1

公开(公告)日：2022-12-22

申请号：US17585031

申请日：2022-01-26

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chung-Chieh Chen ,  Cheng-Hsiung Kuo ,  Yu-Der Chih

IPC: G11C16/28

Abstract: A sense amplifier control system includes a precharge control switch configured to receive a precharge signal. A reference cell is configured to receive a reference word line signal. In a precharge phase, the control switch is controlled in response to the precharge signal to precharge the reference input node to a predetermined precharge level. In a sensing phase subsequent to the pre-charge phase, the trigger circuit is configured to output a triggering signal at the output terminal in response to the reference input node reaching a triggering level.

公开(公告)号：US20220247394A1

公开(公告)日：2022-08-04

申请号：US17162440

申请日：2021-01-29

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chia-Fu Lee ,  Hon-Jarn Lin ,  Yu-Der Chih

IPC: H03K3/356

Abstract: A circuit includes cross coupled invertors including a first invertor and a second inventor. The first invertor and the second invertor are cross coupled at a first data node and a second data node. An input unit is coupled between the cross-coupled invertors and a power node. The input unit controls the cross-coupled invertors in response to a first input signal received at a first input terminal of the input unit and a second input signal received at a second input terminal of the input unit. A first transistor is connected between the power node and a supply node. The first transistor connects the power node to the supply node in response to an enable signal changing to a first value. A second transistor is connected between the power node and ground. The second transistor connects the power node to the ground in response to the enable signal changing to a second value.

公开(公告)号：US20220238155A1

公开(公告)日：2022-07-28

申请号：US17721985

申请日：2022-04-15

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chien-An Lai ,  Chung-Cheng Chou ,  Yu-Der Chih

IPC: G11C13/00 ,  G11C7/10 ,  G11C7/04

Abstract: A memory device includes an array of resistive memory cells with a plurality of word lines connected to the array of resistive memory cells. A voltage compensation controller is configured to determine a word line voltage to be applied to a selected word line of the plurality of word lines. A word line driver is configured apply the determined word line voltage to the selected word line.

公开(公告)号：US11367468B1

公开(公告)日：2022-06-21

申请号：US17186250

申请日：2021-02-26

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chia-Fu Lee ,  Hon-Jarn Lin ,  Yu-Der Chih

IPC: G11C7/02 ,  G11C7/06

Abstract: A sense amplifier is provided. A first terminal of a first invertor is connected to a power node and a second terminal of the first invertor is connected to a cell current source. A first terminal of a second invertor is connected to the power node and a second terminal of the second invertor is connected to a reference current source. The first invertor is cross coupled with the second invertor at a first node and a second node. A pre-charge circuit is connected to the first node and the second node. A first pull up transistor and a second pull up transistor are connected between a supply voltage node and the power node. A signal level detector circuit is connected to the second pull up transistor. The signal level detector circuit switches on the second pull up transistor when a remaining voltage on one of the first node and the second node is below a reference voltage.