公开(公告)号：US20240105605A1

公开(公告)日：2024-03-28

申请号：US17934913

申请日：2022-09-23

Applicant: International Business Machines Corporation

Inventor： Ruilong Xie ,  Daniel Charles Edelstein ,  Rajiv Joshi ,  Ravikumar Ramachandran ,  Eric Miller

IPC: H01L23/528 ,  H01L21/8234 ,  H01L23/48 ,  H01L23/522

CPC classification number: H01L23/5286 ,  H01L21/823475 ,  H01L23/481 ,  H01L23/5226

Abstract: A semiconductor structure includes a front-end-of-line level including a plurality of field effect transistors electrically connected to a back-end-of-line interconnect level. The back-end-of-line interconnect level is located on a first side of the front-end-of-line level. A backside power rail is embedded within a backside interlayer dielectric located on a second side of the front-end-of-line level opposing the first side of the front-end-of-line level. The backside power rail is electrically connected to at least one field effect transistor of the plurality of field effect transistors. At least one backside field effect transistor is formed on a first semiconductor layer disposed, at least in part, above a passive device region. A first side of the passive device region is in contact with the first semiconductor layer and a second side of the passive device region, opposing the first side, is in contact with the back-end-of-line interconnect level.

公开(公告)号：US20230411397A1

公开(公告)日：2023-12-21

申请号：US17807158

申请日：2022-06-16

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Ruilong Xie ,  Julien Frougier ,  Su Chen Fan ,  Ravikumar Ramachandran ,  Oleg Gluschenkov

IPC: H01L27/12 ,  H01L23/522 ,  H01L21/84

CPC classification number: H01L27/1203 ,  H01L23/5226 ,  H01L21/84

Abstract: A microelectronic structure including a stacked transistor having a lower transistor and an upper transistor. A shared contact in contact with a lower source/drain of the first lower transistor and an upper source/drain of the upper transistor. The shared contact includes a silicide layer, a metal plug layer, and a conductive metal layer.

公开(公告)号：US20230130305A1

公开(公告)日：2023-04-27

申请号：US17507385

申请日：2021-10-21

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Ruilong Xie ,  Julien Frougier ,  Su Chen Fan ,  Ravikumar Ramachandran ,  Nicolas Loubet

IPC: H01L29/417 ,  H01L27/092 ,  H01L23/528 ,  H01L29/45 ,  H01L29/40 ,  H01L21/8238

Abstract: A stacked device is provided. The stacked device includes a reduced height active device layer, and a plurality of lower source/drain regions in the reduced height active device layer. The stacked device further includes a lower interlayer dielectric (ILD) layer on the plurality of lower source/drain regions, and a conductive trench spacer in the lower interlayer dielectric (ILD) layer, wherein the conductive trench spacer is adjacent to one of the plurality of lower source/drain regions. The stacked device further includes a top active device layer adjacent to the lower interlayer dielectric (ILD) layer, and an upper source/drain section in the top active device layer. The stacked device further includes a shared contact in electrical connection with the upper source/drain section, the conductive trench spacer, and the one of the plurality of lower source/drain regions.

公开(公告)号：US20190304980A1

公开(公告)日：2019-10-03

申请号：US16444386

申请日：2019-06-18

Applicant: International Business Machines Corporation

Inventor： Ravikumar Ramachandran ,  Reinaldo Ariel Vega

IPC: H01L27/108 ,  H01L29/78 ,  H01L29/66 ,  H01L29/10

Abstract: Embodiments of the present invention provide improved methods and structures for fabrication of capacitor-less DRAM devices, sometimes referred to as ZRAM devices. A channel is formed in a fin-type field effect transistor (finFET) that is comprised of a finned channel portion and a convex channel portion. The finned channel portion may be comprised of a first semiconductor material and the convex channel portion may be comprised of a second, different semiconductor material. In embodiments, a metal gate is disposed around the elongated surface of the channel region, but is not disposed on the short surface of the channel region. A first spacer is disposed adjacent to the gate and in direct physical contact with the short surface of the channel region, and a second spacer is disposed adjacent to the first spacer.

公开(公告)号：US10403628B2

公开(公告)日：2019-09-03

申请号：US14581472

申请日：2014-12-23

Applicant: International Business Machines Corporation

Inventor： Ravikumar Ramachandran ,  Reinaldo Ariel Vega

IPC: H01L29/66 ,  H01L29/78 ,  H01L27/108 ,  H01L29/10 ,  H01L29/165 ,  H01L29/12

Abstract: Embodiments of the present invention provide improved methods and structures for fabrication of capacitor-less DRAM devices, sometimes referred to as ZRAM devices. A channel is formed in a fin-type field effect transistor (finFET) that is comprised of a finned channel portion and a convex channel portion. The finned channel portion may be comprised of a first semiconductor material and the convex channel portion may be comprised of a second, different semiconductor material. In embodiments, a metal gate is disposed around the elongated surface of the channel region, but is not disposed on the short surface of the channel region. A first spacer is disposed adjacent to the gate and in direct physical contact with the short surface of the channel region, and a second spacer is disposed adjacent to the first spacer.

公开(公告)号：US10177039B2

公开(公告)日：2019-01-08

申请号：US15804228

申请日：2017-11-06

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Andrew M. Greene ,  Ravikumar Ramachandran ,  Rajasekhar Venigalla

IPC: H01L21/8234 ,  H01L29/78 ,  H01L29/06 ,  H01L23/535 ,  H01L27/088 ,  H01L21/308 ,  H01L21/311 ,  H01L29/66

Abstract: A dual layer shallow isolation trench region for semiconductor structures including field effect transistors (FETs) and methods for making the same. The first layer of the shallow trench isolation region includes a dielectric material disposed between adjacent FETs. The second layer is an etch resistant material disposed on the dielectric material and has an increased etch resistance relative to the dielectric material. The etch resistant material overlays the shallow trench region to provide the dual layer shallow trench isolation region, which permits self-alignment of contacts to the source and/or drain of FETs.

公开(公告)号：US10083865B2

公开(公告)日：2018-09-25

申请号：US15797941

申请日：2017-10-30

Applicant: International Business Machines Corporation

Inventor： Emre Alptekin ,  Ravikumar Ramachandran ,  Viraj Y. Sardesai ,  Reinaldo A. Vega

IPC: H01L29/76 ,  H01L21/768 ,  H01L29/78 ,  H01L21/321 ,  H01L29/66 ,  H01L29/417 ,  H01L21/283 ,  H01L21/28

CPC classification number: H01L21/76897 ,  H01L21/28008 ,  H01L21/283 ,  H01L21/3212 ,  H01L21/76829 ,  H01L29/41775 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/78

Abstract: A semiconductor structure is provided. The semiconductor includes a gate stack on a substrate. The semiconductor includes a first set of sidewall spacers on opposite sidewalls of the gate stack. The semiconductor includes a flowable dielectric layer on the substrate, covering at least a portion of the first set of sidewall spacers. The semiconductor includes a second set of sidewall spacers next to the first set of sidewall spacers covering an upper portion thereof, the second set of sidewall spacers are directly on top of the flowable dielectric layer. The semiconductor includes a contact next to at least one of the second set of sidewall spacers.

公开(公告)号：US10074562B2

公开(公告)日：2018-09-11

申请号：US15219413

申请日：2016-07-26

Applicant: International Business Machines Corporation

Inventor： Rosa A. Orozco-Teran ,  Ravikumar Ramachandran ,  John A. Fitzsimmons ,  Russell H. Arndt ,  David L. Rath

IPC: H01L21/768 ,  H01L29/49 ,  H01L29/45 ,  H01L21/28 ,  H01L23/522 ,  H01L23/532 ,  H01L29/417 ,  H01L29/423 ,  H01L23/528 ,  H01L29/78

CPC classification number: H01L21/76897 ,  H01L21/28079 ,  H01L21/76805 ,  H01L21/76814 ,  H01L21/76816 ,  H01L21/76831 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/53295 ,  H01L29/41775 ,  H01L29/42372 ,  H01L29/45 ,  H01L29/4958 ,  H01L29/78 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Embodiments of present invention provide a method of forming a semiconductor structure. The method includes forming a semiconductor structure having a first metal layer and a plurality of dielectric layers on top of the first metal layer; creating one or more openings through the plurality of dielectric layers to expose the first metal layer underneath the plurality of dielectric layers; causing the one or more openings to expand downward into the first metal layer and expand horizontally into areas underneath the plurality of dielectric layers; applying a layer of lining material in lining sidewalls of the one or more openings inside the plurality of dielectric layers; and filling the expanded one or more openings with a conductive material.

公开(公告)号：US20180226298A1

公开(公告)日：2018-08-09

申请号：US15427423

申请日：2017-02-08

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Andrew M. Greene ,  Ravikumar Ramachandran ,  Rajasekhar Venigalla

IPC: H01L21/8234 ,  H01L29/06 ,  H01L23/535 ,  H01L29/78 ,  H01L27/088 ,  H01L21/308 ,  H01L21/311 ,  H01L29/66

CPC classification number: H01L21/823481 ,  H01L21/3081 ,  H01L21/31111 ,  H01L21/823431 ,  H01L21/823475 ,  H01L23/535 ,  H01L27/0886 ,  H01L29/0653 ,  H01L29/66795 ,  H01L29/785

Abstract: A dual layer shallow isolation trench region for semiconductor structures including field effect transistors (FETs) and methods for making the same. The first layer of the shallow trench isolation region includes a dielectric material disposed between adjacent FETs. The second layer is an etch resistant material disposed on the dielectric material and has an increased etch resistance relative to the dielectric material. The etch resistant material overlays the shallow trench region to provide the dual layer shallow trench isolation region, which permits self-alignment of contacts to the source and/or drain of FETs.

公开(公告)号：US20180211948A1

公开(公告)日：2018-07-26

申请号：US15802956

申请日：2017-11-03

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Albert M. Chu ,  Myung-Hee Na ,  Ravikumar Ramachandran

IPC: H01L27/02 ,  G06F17/50

Abstract: A method is presented for forming a layout of a MOSFET (metal oxide semiconductor field effect transistor) circuit. The method includes forming a plurality of gate conductors, forming a plurality of active areas, and forming at least one gate contact (CB contact) within an active region of the plurality of active regions. The method further includes placing a marker over the at least one gate contact to identify a location of the at least one gate contact. Additionally, a distance between the at least one gate contact and at least one TS contact is optimized based on device specifications.