公开(公告)号：US20200090946A1

公开(公告)日：2020-03-19

申请号：US16132837

申请日：2018-09-17

Applicant: Applied Materials, Inc.

Inventor： Bhargav S. CITLA ,  Jethro TANNOS ,  Jingyi LI ,  Douglas A. BUCHBERGER, JR. ,  Zhong Qiang HUA ,  Srinivas D. NEMANI ,  Ellie Y. YIEH

IPC: H01L21/311 ,  H01L21/762 ,  H01L21/67 ,  H01L21/3065 ,  H01J37/32

Abstract: Embodiments of the present invention provide an apparatus and methods for depositing a dielectric material using RF bias pulses along with remote plasma source deposition for manufacturing semiconductor devices, particularly for filling openings with high aspect ratios in semiconductor applications. In one embodiment, a method of depositing a dielectric material includes providing a gas mixture into a processing chamber having a substrate disposed therein, forming a remote plasma in a remote plasma source and delivering the remote plasma to an interior processing region defined in the processing chamber, applying a RF bias power to the processing chamber in pulsed mode, and forming a dielectric material in an opening defined in a material layer disposed on the substrate in the presence of the gas mixture and the remote plasma.

公开(公告)号：US20190311896A1

公开(公告)日：2019-10-10

申请号：US16354654

申请日：2019-03-15

Applicant: Applied Materials, Inc.

Inventor： Mihaela BALSEANU ,  Srinivas D. NEMANI ,  Mei-Yee SHEK ,  Ellie Y. YIEH

IPC: H01L21/02 ,  H01L29/66 ,  C23C16/455 ,  C23C16/46 ,  C23C16/34 ,  C23C16/36

Abstract: A method for forming a thermally stable spacer layer is disclosed. The method includes first disposing a substrate in an internal volume of a processing chamber. The substrate has a film formed thereon, the film including silicon, carbon, nitrogen, and hydrogen. Next, high pressure steam is introduced into the processing chamber. The film is exposed to the high pressure steam to convert the film to reacted film, the reacted film including silicon, carbon, oxygen, and hydrogen.

公开(公告)号：US20190187563A1

公开(公告)日：2019-06-20

申请号：US16272962

申请日：2019-02-11

Applicant: Applied Materials, Inc.

Inventor： Viachslav BABAYAN ,  Douglas A. BUCHBERGER, JR. ,  Qiwei LIANG ,  Ludovic GODET ,  Srinivas D. NEMANI ,  Daniel J. WOODRUFF ,  Randy HARRIS ,  Robert B. MOORE

IPC: G03F7/20 ,  G03F7/38 ,  H01L21/687 ,  G03F7/16 ,  G03F7/26

CPC classification number: G03F7/2035 ,  G03F7/168 ,  G03F7/26 ,  G03F7/38 ,  H01L21/68764

Abstract: Embodiments described herein relate to methods and apparatus for performing immersion field guided post exposure bake processes. Embodiments of apparatus described herein include a chamber body defining a processing volume. A pedestal may be disposed within the processing volume and a first electrode may be coupled to the pedestal. A moveable stem may extend through the chamber body opposite the pedestal and a second electrode may be coupled to the moveable stem. In certain embodiments, a fluid containment ring may be coupled to the pedestal and a dielectric containment ring may be coupled to the second electrode.

公开(公告)号：US20190103278A1

公开(公告)日：2019-04-04

申请号：US16189429

申请日：2018-11-13

Applicant: Applied Materials, Inc. ,  The Regents of the University of California

Inventor： Raymond HUNG ,  Namsung KIM ,  Srinivas D. NEMANI ,  Ellie Y. YIEH ,  Jong CHOI ,  Christopher AHLES ,  Andrew KUMMEL

IPC: H01L21/285 ,  H01L21/311 ,  H01L21/324 ,  C23C16/42 ,  C23C16/455 ,  C23C16/46

Abstract: Embodiments of the disclosure relate to selective metal silicide deposition methods. In one embodiment, a substrate having a silicon containing surface is heated and the silicon containing surface is hydrogen terminated. The substrate is exposed to sequential cycles of a MoF6 precursor and a Si2H6 precursor which is followed by an additional Si2H6 overdose exposure to selectively deposit a MoSix material comprising MoSi2 on the silicon containing surface of the substrate. Methods described herein also provide for selective native oxide removal which enables removal of native oxide material without etching bulk oxide materials.

公开(公告)号：US20180209035A1

公开(公告)日：2018-07-26

申请号：US15857384

申请日：2017-12-28

Applicant: Applied Materials, Inc.

Inventor： Jingjing LIU ,  Ludovic GODET ,  Srinivas D. NEMANI ,  Yongmei CHEN ,  Anantha K. SUBRAMANI

IPC: C23C14/34 ,  H01L21/265 ,  H01J37/34 ,  H01J37/32 ,  C23C14/50 ,  C23C14/35 ,  C23C14/48

Abstract: Embodiments of the present disclosure provide a sputtering chamber with in-situ ion implantation capability. In one embodiment, the sputtering chamber comprises a target, an RF and a DC power supplies coupled to the target, a support body comprising a flat substrate receiving surface, a bias power source coupled to the support body, a pulse controller coupled to the bias power source, wherein the pulse controller applies a pulse control signal to the bias power source such that the bias power is delivered either in a regular pulsed mode having a pulse duration of about 100-200 microseconds and a pulse repetition frequency of about 1-200 Hz, or a high frequency pulsed mode having a pulse duration of about 100-300 microseconds and a pulse repetition frequency of about 200 Hz to about 20 KHz, and an exhaust assembly having a concentric pumping port formed through a bottom of the processing chamber.

公开(公告)号：US20180136569A1

公开(公告)日：2018-05-17

申请号：US15811341

申请日：2017-11-13

Applicant: Applied Materials, Inc.

Inventor： Mangesh BANGAR ,  Srinivas D. NEMANI ,  Steve G. GHANAYEM ,  Ellie Y. YIEH

IPC: G03F7/20

CPC classification number: G03F7/70633

Abstract: Embodiments disclosed herein relate to methods and systems for correcting overlay errors on a surface of a substrate. A processor performs a measurement process on a substrate to obtain an overlay error map. The processor determines an order of treatment for the substrate based on the overlay error map. The order of treatment includes one or more treatment processes. The processor generates a process recipe for a treatment process of the one or more treatment processes in the order of treatment. The processor provides the process recipe to a substrate treatment apparatus.

公开(公告)号：US20170287752A1

公开(公告)日：2017-10-05

申请号：US15445303

申请日：2017-02-28

Applicant: Applied Materials, Inc.

Inventor： Ludovic GODET ,  Mehdi VAEZ-IRAVANI ,  Todd EGAN ,  Mangesh BANGAR ,  Concetta RICCOBENE ,  Abdul Aziz KHAJA ,  Srinivas D. NEMANI ,  Ellie Y. YIEH ,  Sean S. KANG

IPC: H01L21/67 ,  H01L21/265 ,  H01L21/66

CPC classification number: H01L21/67259 ,  H01L21/265 ,  H01L21/67167 ,  H01L21/67196 ,  H01L21/67201 ,  H01L21/67207 ,  H01L21/67213 ,  H01L21/67288 ,  H01L22/20

Abstract: Embodiments of the disclosure provide an integrated system for performing a measurement process and a lithographic overlay error correction process on a semiconductor substrate in a single processing system. In one embodiment, a processing system includes at least a load lock chamber, a transfer chamber coupled to the load lock chamber, an ion implantation processing chamber coupled to or in the transfer chamber, and a metrology tool coupled to the transfer chamber, wherein the metrology tool is adapted to obtain stress profile or an overlay error on a substrate disposed in the metrology tool.

公开(公告)号：US20170154776A1

公开(公告)日：2017-06-01

申请号：US15432368

申请日：2017-02-14

Applicant: Applied Materials, Inc.

Inventor： Ludovic GODET ,  Srinivas D. NEMANI ,  Erica CHEN ,  Jun XUE ,  Ellie Y. YIEH ,  Gary E. DICKERSON

IPC: H01L21/033 ,  H01L21/3105

CPC classification number: H01L21/0337 ,  H01J2237/24528 ,  H01L21/0332 ,  H01L21/0335 ,  H01L21/3105 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/31155 ,  H01L21/32 ,  H01L21/76205 ,  H01L21/7624 ,  H01L21/823431 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/0924 ,  H01L27/10879 ,  H01L27/1211 ,  H01L29/66795 ,  H01L29/66803 ,  H01L29/7831

Abstract: Embodiments of the present disclosure relate to precision material modification of three dimensional (3D) features or advanced processing techniques. Directional ion implantation methods are utilized to selectively modify desired regions of a material layer to improve etch characteristics of the modified material. For example, a modified region of a material layer may exhibit improved etch selectivity relative to an unmodified region of the material layer. Methods described herein are useful for manufacturing 3D hardmasks which may be advantageously utilized in various integration schemes, such as fin isolation and gate-all-around, among others. Multiple directional ion implantation processes may also be utilized to form dopant gradient profiles within a modified layer to further influence etching processes.

公开(公告)号：US20170092502A1

公开(公告)日：2017-03-30

申请号：US15240410

申请日：2016-08-18

Applicant: Applied Materials, Inc.

Inventor： Bencherki MEBARKI ,  Ellie Y. YIEH ,  Mehul B. NAIK ,  Srinivas D. NEMANI

IPC: H01L21/285 ,  H01L21/768 ,  H01L23/528 ,  H01L21/02 ,  H01L21/324

CPC classification number: H01L21/28518 ,  C23C16/42 ,  C23C16/4418 ,  C23C16/511 ,  C23C16/56 ,  H01L21/02532 ,  H01L21/28556 ,  H01L21/324 ,  H01L21/76864 ,  H01L21/76885 ,  H01L21/76889 ,  H01L23/528 ,  H01L23/53271

Abstract: Implementations described herein generally relate to methods of selective deposition of metal silicides. More specifically, implementations described herein generally relate to methods of forming nickel silicide nanowires for semiconductor applications. In one implementation, a method of processing a substrate is provided. The method comprises forming a silicon-containing layer on a surface of a substrate, forming a metal-containing layer comprising a transition metal on the silicon-containing layer, forming a confinement layer on exposed surfaces of the metal-containing layer and annealing the substrate at a temperature of less than 400 degrees Celsius to form a metal silicide layer from the silicon-containing layer and the metal-containing layer, wherein the confinement layer inhibits formation of metal-rich metal silicide phases.

公开(公告)号：US20170053797A1

公开(公告)日：2017-02-23

申请号：US15346306

申请日：2016-11-08

Applicant: Applied Materials, Inc.

Inventor： Srinivas D. NEMANI ,  Ellie Y. YIEH ,  Ludovic GODET ,  Yin FAN

IPC: H01L21/02 ,  H01L29/66 ,  H01J37/32 ,  H01L21/3115

CPC classification number: H01L21/02304 ,  H01J37/32357 ,  H01J37/32403 ,  H01J37/32422 ,  H01L21/0228 ,  H01L21/02321 ,  H01L21/0234 ,  H01L21/31155 ,  H01L29/66795 ,  H01L29/66803

Abstract: Methods for forming fin structure with desired materials formed on different locations of the fin structure using a selective deposition process for three dimensional (3D) stacking of fin field effect transistor (FinFET) for semiconductor chips are provided. In one embodiment, a method of forming a structure with desired materials on a substrate includes forming a patterned self-assembled monolayer on a circumference of a structure formed on a substrate, wherein the patterned self-assembled monolayer includes a treated layer formed among a self-assembled monolayer, and performing an atomic layer deposition process to form a material layer predominantly on the self-assembled monolayer from the patterned self-assembled monolayer.

Abstract translation: 提供了使用用于半导体芯片的鳍式场效应晶体管（FinFET）的三维（3D）堆叠的选择性沉积工艺在翅片结构的不同位置形成所需材料的翅片结构的方法。 在一个实施方案中，在衬底上形成具有期望材料的结构的方法包括在形成在衬底上的结构的圆周上形成图案化的自组装单层，其中所述图案化的自组装单层包括在自身中形成的处理层 并且执行原子层沉积工艺，以从图案化的自组装单层形成主要在自组装单层上的材料层。