公开(公告)号：US20180101103A1

公开(公告)日：2018-04-12

申请号：US15829809

申请日：2017-12-01

Applicant: APPLIED MATERIALS, INC.

Inventor： Mangesh BANGAR ,  Bruce E. ADAMS ,  Kelly E. HOLLAR ,  Abhilash J. MAYUR ,  Huixiong DAI ,  Jaujiun CHEN

IPC: G03F7/20

CPC classification number: G03F7/70633

Abstract: A calibration curve for a wafer comprising a layer on a substrate is determined. The calibration curve represents a local parameter change as a function of a treatment parameter associated with a wafer exposure to a light. The local parameter of the wafer is measured. An overlay error is determined based on the local parameter of the wafer. A treatment map is computed based on the calibration curve to correct the overlay error for the wafer. The treatment map represents the treatment parameter as a function of a location on the wafer.

公开(公告)号：US20200233307A1

公开(公告)日：2020-07-23

申请号：US16600101

申请日：2019-10-11

Applicant: Applied Materials, Inc.

Inventor： Huixiong DAI ,  Mangesh BANGAR ,  Christopher S. NGAI ,  Srinivas D. NEMANI ,  Ellie Y. YIEH ,  Steven Hiloong WELCH

IPC: G03F7/16 ,  G03F7/09 ,  G03F7/20

Abstract: Methods and apparatuses for minimizing line edge/width roughness in lines formed by photolithography are provided. In one example, a method of processing a substrate includes applying a photoresist layer comprising a photoacid generator to on a multi-layer disposed on a substrate, wherein the multi-layer comprises an underlayer formed from an organic material, inorganic material, or a mixture of organic and inorganic materials, exposing a first portion of the photoresist layer unprotected by a photomask to a radiation light in a lithographic exposure process, and applying an electric field or a magnetic field to alter movement of photoacid generated from the photoacid generator substantially in a vertical direction.

公开(公告)号：US20190094179A1

公开(公告)日：2019-03-28

申请号：US16041429

申请日：2018-07-20

Applicant: Applied Materials, Inc.

Inventor： Mangesh BANGAR ,  Joseph R. JOHNSON

IPC: G01N27/447 ,  C12Q1/6869 ,  G01N33/487

Abstract: Aspects disclosed herein relate to methods of high-volume manufacturing of an array of biological sensing devices on a substrate, each of the biological sensing devices having a vertical or horizontal membrane having one or more solid-state nanopores therethrough, and methods for simple fluidic addressing of each nanopore. In one aspect, a method for forming a nanopore by applying a voltage from a positive electrode to a negative electrode through a free-standing membrane is disclosed. In other aspects, methods for forming a plurality of nanopores on a wafer are disclosed. In another aspect, a single-sided processing method for forming a nanopore device is disclosed to provide a device having baths on either side of a nanopore, which are addressable from a single side of the substrate. In yet another aspect, a method for fluidically addressing a plurality of nanopore devices is disclosed.

公开(公告)号：US20180136569A1

公开(公告)日：2018-05-17

申请号：US15811341

申请日：2017-11-13

Applicant: Applied Materials, Inc.

Inventor： Mangesh BANGAR ,  Srinivas D. NEMANI ,  Steve G. GHANAYEM ,  Ellie Y. YIEH

IPC: G03F7/20

CPC classification number: G03F7/70633

Abstract: Embodiments disclosed herein relate to methods and systems for correcting overlay errors on a surface of a substrate. A processor performs a measurement process on a substrate to obtain an overlay error map. The processor determines an order of treatment for the substrate based on the overlay error map. The order of treatment includes one or more treatment processes. The processor generates a process recipe for a treatment process of the one or more treatment processes in the order of treatment. The processor provides the process recipe to a substrate treatment apparatus.

公开(公告)号：US20170287752A1

公开(公告)日：2017-10-05

申请号：US15445303

申请日：2017-02-28

Applicant: Applied Materials, Inc.

Inventor： Ludovic GODET ,  Mehdi VAEZ-IRAVANI ,  Todd EGAN ,  Mangesh BANGAR ,  Concetta RICCOBENE ,  Abdul Aziz KHAJA ,  Srinivas D. NEMANI ,  Ellie Y. YIEH ,  Sean S. KANG

IPC: H01L21/67 ,  H01L21/265 ,  H01L21/66

CPC classification number: H01L21/67259 ,  H01L21/265 ,  H01L21/67167 ,  H01L21/67196 ,  H01L21/67201 ,  H01L21/67207 ,  H01L21/67213 ,  H01L21/67288 ,  H01L22/20

Abstract: Embodiments of the disclosure provide an integrated system for performing a measurement process and a lithographic overlay error correction process on a semiconductor substrate in a single processing system. In one embodiment, a processing system includes at least a load lock chamber, a transfer chamber coupled to the load lock chamber, an ion implantation processing chamber coupled to or in the transfer chamber, and a metrology tool coupled to the transfer chamber, wherein the metrology tool is adapted to obtain stress profile or an overlay error on a substrate disposed in the metrology tool.