公开(公告)号：US20170154776A1

公开(公告)日：2017-06-01

申请号：US15432368

申请日：2017-02-14

Applicant: Applied Materials, Inc.

Inventor： Ludovic GODET ,  Srinivas D. NEMANI ,  Erica CHEN ,  Jun XUE ,  Ellie Y. YIEH ,  Gary E. DICKERSON

IPC: H01L21/033 ,  H01L21/3105

CPC classification number: H01L21/0337 ,  H01J2237/24528 ,  H01L21/0332 ,  H01L21/0335 ,  H01L21/3105 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/31155 ,  H01L21/32 ,  H01L21/76205 ,  H01L21/7624 ,  H01L21/823431 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/0924 ,  H01L27/10879 ,  H01L27/1211 ,  H01L29/66795 ,  H01L29/66803 ,  H01L29/7831

Abstract: Embodiments of the present disclosure relate to precision material modification of three dimensional (3D) features or advanced processing techniques. Directional ion implantation methods are utilized to selectively modify desired regions of a material layer to improve etch characteristics of the modified material. For example, a modified region of a material layer may exhibit improved etch selectivity relative to an unmodified region of the material layer. Methods described herein are useful for manufacturing 3D hardmasks which may be advantageously utilized in various integration schemes, such as fin isolation and gate-all-around, among others. Multiple directional ion implantation processes may also be utilized to form dopant gradient profiles within a modified layer to further influence etching processes.

公开(公告)号：US20160163546A1

公开(公告)日：2016-06-09

申请号：US14613545

申请日：2015-02-04

Applicant: Applied Materials, Inc.

Inventor： Ludovic GODET ,  Srinivas D. NEMANI ,  Erica CHEN ,  Jun XUE ,  Ellie Y. YIEH ,  Gary E. DICKERSON

IPC: H01L21/033 ,  H01L21/762 ,  H01L23/00 ,  H01L21/84

CPC classification number: H01L21/0337 ,  H01J2237/24528 ,  H01L21/0332 ,  H01L21/0335 ,  H01L21/3105 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/31155 ,  H01L21/32 ,  H01L21/76205 ,  H01L21/7624 ,  H01L21/823431 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/0924 ,  H01L27/10879 ,  H01L27/1211 ,  H01L29/66795 ,  H01L29/66803 ,  H01L29/7831

Abstract: Embodiments of the present disclosure relate to precision material modification of three dimensional (3D) features or advanced processing techniques. Directional ion implantation methods are utilized to selectively modify desired regions of a material layer to improve etch characteristics of the modified material. For example, a modified region of a material layer may exhibit improved etch selectivity relative to an unmodified region of the material layer. Methods described herein are useful for manufacturing 3D hardmasks which may be advantageously utilized in various integration schemes, such as fin isolation and gate-all-around, among others. Multiple directional ion implantation processes may also be utilized to form dopant gradient profiles within a modified layer to further influence etching processes.

Abstract translation: 本公开的实施例涉及三维（3D）特征或高级处理技术的精密材料修改。 方向离子注入方法用于选择性地修饰材料层的所需区域以改善改性材料的蚀刻特性。 例如，材料层的改性区域相对于材料层的未改性区域可以表现出改进的蚀刻选择性。 本文描述的方法可用于制造3D硬掩模，其可以有利地用于各种集成方案中，例如翅片隔离和门全部等。 多方向离子注入工艺也可用于在改性层内形成掺杂剂梯度分布，以进一步影响蚀刻工艺。

公开(公告)号：US20170271181A1

公开(公告)日：2017-09-21

申请号：US15584767

申请日：2017-05-02

Applicant: Applied Materials, Inc.

Inventor： Gary E. DICKERSON ,  Seng (victor) Keong LIM ,  Samer BANNA ,  Gregory KIRK ,  Mehdi VAEZ-IRAVANI

IPC: H01L21/67 ,  H01L21/324

CPC classification number: H01L21/67248 ,  H01L21/0273 ,  H01L21/324 ,  H01L21/67103 ,  H01L21/67115 ,  H01L21/67253 ,  H01L21/6831 ,  H01L22/12

Abstract: Embodiments of the present disclosure relate to an apparatus and a method for reducing the adverse effects of exposing portions of an integrated circuit (IC) device to various forms of radiation during one or more operations found within the IC formation processing sequence by controlling the environment surrounding and temperature of an IC device during one or more parts of the IC formation processing sequence. The provided energy may include the delivery of radiation to a surface of a formed or a partially formed IC device during a deposition, etching, inspection or post-processing process operation. In some embodiments of the disclosure, the temperature of the substrate on which the IC device is formed is controlled to a temperature that is below room temperature (e.g.,

公开(公告)号：US20160276227A1

公开(公告)日：2016-09-22

申请号：US15075094

申请日：2016-03-18

Applicant: Applied Materials, Inc.

Inventor： Gary E. DICKERSON ,  Seng (victor) Keong LIM ,  Samer BANNA ,  Gregory KIRK ,  Mehdi VAEZ-IRAVANI

IPC: H01L21/66 ,  H01L21/683 ,  H01L21/67 ,  H01L21/324 ,  H01L21/027

CPC classification number: H01L21/67248 ,  H01L21/0273 ,  H01L21/324 ,  H01L21/67103 ,  H01L21/67115 ,  H01L21/67253 ,  H01L21/6831 ,  H01L22/12

Abstract: Embodiments of the present disclosure relate to an apparatus and a method for reducing the adverse effects of exposing portions of an integrated circuit (IC) device to various forms of radiation during one or more operations found within the IC formation processing sequence by controlling the environment surrounding and temperature of an IC device during one or more parts of the IC formation processing sequence. The provided energy may include the delivery of radiation to a surface of a formed or a partially formed IC device during a deposition, etching, inspection or post-processing process operation. In some embodiments of the disclosure, the temperature of the substrate on which the IC device is formed is controlled to a temperature that is below room temperature (e.g.,

Abstract translation: 本公开的实施例涉及一种用于在通过控制周围环境的IC形成处理序列期间发现的一个或多个操作期间减少将集成电路（IC）装置的部分暴露于各种形式的辐射的不良影响的装置和方法 以及在IC形成处理序列的一个或多个部分期间的IC器件的温度。 提供的能量可以包括在沉积，蚀刻，检查或后处理过程操作期间将辐射传送到形成的或部分形成的IC器件的表面。 在本公开的一些实施例中，将IC器件形成的衬底的温度控制在IC形成处理序列的一个或多个部分期间低于室温（例如，<20℃）的温度 。

公开(公告)号：US20230187222A1

公开(公告)日：2023-06-15

申请号：US17549325

申请日：2021-12-13

Applicant: Applied Materials, Inc.

Inventor： Mukhles SOWWAN ,  Samer BANNA ,  Nirmalya MAITY ,  Nalamasu OMKARAM ,  Gary E. DICKERSON

IPC: H01L21/48 ,  H01L23/14 ,  H01L23/498

CPC classification number: H01L21/486 ,  H01L21/4857 ,  H01L23/147 ,  H01L23/49822

Abstract: The present disclosure relates to semiconductor core assemblies and methods of forming the same. The semiconductor core assemblies described herein may be utilized to form semiconductor package assemblies, printed circuit board (PCB) assemblies, PCB spacer assemblies, chip carrier assemblies, intermediate carrier assemblies (e.g., for graphics cards), and the like. In one embodiment, a substrate core (e.g., a core structure) is implanted with dopants to achieve a desired bulk resistivity or conductivity. One or more conductive interconnections are formed in the substrate core and one or more redistribution layers are formed on surfaces thereof. The substrate core may thereafter be utilized as a core structure for a semiconductor package, PCB, PCB spacer, chip carrier, intermediate carrier, or the like.

公开(公告)号：US20220177821A1

公开(公告)日：2022-06-09

申请号：US17111359

申请日：2020-12-03

Applicant: Applied Materials, Inc.

Inventor： Samer BANNA ,  Mukhles SOWWAN ,  Gary E. DICKERSON

IPC: C12M3/00 ,  C12M1/00

Abstract: Methods and apparatus of bioreactors for therapeutic cells manufacturing are provided herein. In some embodiments, a bioreactor includes: an upper bioreactor reservoir configured to perform multiple cell therapy manufacturing process steps including genetic modification and expansion to a plurality of cells disposed therein, wherein the upper bioreactor reservoir includes a plurality of ports for delivering fluids into and out of the upper bioreactor reservoir; a lower bioreactor compartment configured to hold a suspension comprising a molecular species; and a membrane disposed between the lower bioreactor compartment and the upper bioreactor reservoir, wherein the membrane includes a plurality of micro-straws extending through the membrane and into the upper bioreactor reservoir to transfect the plurality of cells with the molecular species.

公开(公告)号：US20150255243A1

公开(公告)日：2015-09-10

申请号：US14641071

申请日：2015-03-06

Applicant: Applied Materials, Inc.

Inventor： Ludovic GODET ,  Ellie Y. YIEH ,  Srinivas D. NEMANI ,  Gary E. DICKERSON ,  Svetlana B. RADOVANOV ,  Adam BRAND

IPC: H01J37/147 ,  H01J37/08 ,  H01J37/32

CPC classification number: H01J37/32091 ,  H01J37/32422 ,  H01J37/32568 ,  H01J37/32899

Abstract: Embodiments of the disclosure provide apparatus and methods for modifying a surface of a substrate using a plasma modification process. In one embodiment, a process generally includes the removal and/or redistribution of a portion of an exposed surface of the substrate by use of an energetic particle beam while the substrate is disposed within a particle beam modification apparatus. Embodiments may also provide a plasma modification process that includes one or more pre-planarization processing steps and/or one or more post-planarization processing steps that are all performed within one processing system. Some embodiments may provide an apparatus and methods for planarizing a surface of a substrate by performing all of the plasma modification processes within either the same processing chamber, the same processing system or within processing chambers found in two or more processing systems.

Abstract translation: 本公开的实施例提供了使用等离子体修饰工艺来修饰衬底的表面的装置和方法。 在一个实施方案中，方法通常包括通过使用能量粒子束来去除和/或重新分配衬底的暴露表面的一部分，同时将衬底设置在粒子束修改设备内。 实施例还可以提供等离子体修饰过程，其包括一个或多个预平面化处理步骤和/或一个或多个在一个处理系统内执行的后平面化处理步骤。 一些实施例可以提供用于通过执行在两个或更多个处理系统中找到的相同处理室，相同处理系统或处理室内的所有等离子体修饰过程来平坦化衬底表面的装置和方法。