公开(公告)号：US20160141202A1

公开(公告)日：2016-05-19

申请号：US14597149

申请日：2015-01-14

Applicant: Applied Materials, Inc.

Inventor： Jun XUE ,  Ludovic GODET ,  Erica CHEN ,  Srinivas D. NEMANI ,  Ellie Y. YIEH

IPC: H01L21/768 ,  H01L21/3115 ,  H01L21/311 ,  H01L21/223

CPC classification number: H01L21/7682 ,  H01J37/32357 ,  H01J37/32366 ,  H01J37/32412 ,  H01J37/32422 ,  H01L21/2236 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/31155 ,  H01L21/768 ,  H01L21/76825 ,  H01L23/5222

Abstract: Methods for forming air gaps in an interconnection structure with desired materials formed on different locations of the interconnection structure using an ion implantation process to define an etching boundary followed by an etching process for semiconductor devices are provided. In one embodiment, a method for forming air gaps in an interconnection structure on a substrate, the method includes implanting ions in a first region of an insulating material disposed on a substrate, leaving a second region without implanted ions, the second region having a first surface interfaced with the first region and a second surface interfaced with the substrate, and performing an etching process to selectively etch the second region away from the substrate, forming an air gap between the first region and the substrate.

Abstract translation: 提供了使用离子注入工艺形成在互连结构的不同位置上形成的所需材料的互连结构中的空气间隙以限定蚀刻边界，然后进行半导体器件的蚀刻工艺的方法。 在一个实施例中，一种用于在衬底上形成互连结构中的气隙的方法，所述方法包括将离子注入设置在衬底上的绝缘材料的第一区域中，留下没有注入离子的第二区域，第二区域具有第一 与第一区域接合的表面和与衬底接合的第二表面，以及执行蚀刻工艺以选择性地蚀刻第二区域远离衬底，在第一区域和衬底之间形成气隙。

公开(公告)号：US20180102248A1

公开(公告)日：2018-04-12

申请号：US15831342

申请日：2017-12-04

Applicant: APPLIED MATERIALS, INC.

Inventor： Jun XUE ,  Ludovic GODET ,  Martin A. HILKENE ,  Matthew D. SCOTNEY-CASTLE

IPC: H01L21/02 ,  C23C14/04 ,  H01J37/32 ,  H01L21/033

CPC classification number: H01L21/02527 ,  C23C14/046 ,  H01J37/321 ,  H01J37/32422 ,  H01L21/02274 ,  H01L21/02381 ,  H01L21/0243 ,  H01L21/02532 ,  H01L21/02631 ,  H01L21/02639 ,  H01L21/033 ,  H01L21/67253

Abstract: Ion species are supplied to a workpiece comprising a pattern layer over a substrate. A material layer is deposited on the pattern layer using an implantation process of the ion species. In one embodiment, the deposited material layer has an etch selectivity to the pattern layer. In one embodiment, a trench is formed on the pattern layer. The trench comprises a bottom and a sidewall. The material layer is deposited into the trench using the ion implantation process. The material layer is deposited on the bottom of the trench in a direction along the sidewall.

公开(公告)号：US20170062216A1

公开(公告)日：2017-03-02

申请号：US15348170

申请日：2016-11-10

Applicant: Applied Materials, Inc.

Inventor： Yongmei CHEN ,  Christopher S. NGAI ,  Jingjing LIU ,  Jun XUE ,  Chentsau YING ,  Ludovic GODET

IPC: H01L21/033 ,  H01L27/115

CPC classification number: H01L21/0332 ,  C23C16/26 ,  C23C16/27 ,  C23C16/274 ,  C23C16/279 ,  H01L21/02115 ,  H01L21/02274 ,  H01L21/0335 ,  H01L21/0337 ,  H01L21/31111 ,  H01L21/31122 ,  H01L21/31144 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11582 ,  H01L29/49 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/4975 ,  H01L29/51 ,  H01L29/518

Abstract: A nanocrystalline diamond layer for use in forming a semiconductor device and methods for using the same are disclosed herein. The device can include a substrate with a processing surface and a supporting surface, a device layer formed on the processing surface and a nanocrystalline diamond layer formed on the processing layer, the nanocrystalline diamond layer having an average grain size of between 2 nm and 5 nm. The method can include positioning a substrate in a process chamber, depositing a device layer on a processing surface, depositing a nanocrystalline diamond layer on the device layer, the nanocrystalline diamond layer having an average grain size of between 2 nm and 5 nm, patterning and etching the nanocrystalline diamond layer, etching the device layer to form a feature and ashing the nanocrystalline diamond layer from the surface of the device layer.

Abstract translation: 本文公开了一种用于形成半导体器件的纳米晶体金刚石层及其使用方法。 该器件可以包括具有处理表面和支撑表面的衬底，形成在处理表面上的器件层和形成在处理层上的纳米晶体金刚石层，该纳米晶体金刚石层的平均晶粒尺寸在2nm和5nm之间 。 该方法可以包括将衬底定位在处理室中，在处理表面上沉积器件层，在器件层上沉积纳米晶体金刚石层，平均晶粒尺寸在2nm和5nm之间的纳米晶体金刚石层，图案化和 蚀刻纳米晶体金刚石层，蚀刻器件层以形成特征并从器件层的表面灰化纳米晶体金刚石层。

公开(公告)号：US20170200587A1

公开(公告)日：2017-07-13

申请号：US15399084

申请日：2017-01-05

Applicant: Applied Materials, Inc.

Inventor： Ludovic GODET ,  Jun XUE ,  Sang Ki NAM

IPC: H01J37/32 ,  H01L21/3065

CPC classification number: H01J37/32082 ,  H01J37/32357 ,  H01J37/32422 ,  H01J37/3244 ,  H01J37/32449 ,  H01J37/32532 ,  H01J37/32559 ,  H01J37/32568 ,  H01J2237/334 ,  H01L21/3065

Abstract: Implementations described herein relate to apparatus and methods for performing atomic layer etching (ALE). Pulsed plasma generation and subsequent bias application to plasma afterglow may provide for improved ALE characteristics. Apparatus described herein provide for plasma generation from one or more plasma sources and biasing of plasma afterglow to facilitate material removal from a substrate.

公开(公告)号：US20170154776A1

公开(公告)日：2017-06-01

申请号：US15432368

申请日：2017-02-14

Applicant: Applied Materials, Inc.

Inventor： Ludovic GODET ,  Srinivas D. NEMANI ,  Erica CHEN ,  Jun XUE ,  Ellie Y. YIEH ,  Gary E. DICKERSON

IPC: H01L21/033 ,  H01L21/3105

CPC classification number: H01L21/0337 ,  H01J2237/24528 ,  H01L21/0332 ,  H01L21/0335 ,  H01L21/3105 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/31155 ,  H01L21/32 ,  H01L21/76205 ,  H01L21/7624 ,  H01L21/823431 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/0924 ,  H01L27/10879 ,  H01L27/1211 ,  H01L29/66795 ,  H01L29/66803 ,  H01L29/7831

Abstract: Embodiments of the present disclosure relate to precision material modification of three dimensional (3D) features or advanced processing techniques. Directional ion implantation methods are utilized to selectively modify desired regions of a material layer to improve etch characteristics of the modified material. For example, a modified region of a material layer may exhibit improved etch selectivity relative to an unmodified region of the material layer. Methods described herein are useful for manufacturing 3D hardmasks which may be advantageously utilized in various integration schemes, such as fin isolation and gate-all-around, among others. Multiple directional ion implantation processes may also be utilized to form dopant gradient profiles within a modified layer to further influence etching processes.

公开(公告)号：US20160194758A1

公开(公告)日：2016-07-07

申请号：US14635589

申请日：2015-03-02

Applicant: Applied Materials, Inc.

Inventor： Srinivas D. NEMANI ,  Erica CHEN ,  Ludovic GODET ,  Jun XUE ,  Ellie Y. YIEH

IPC: C23C16/56 ,  C23C16/32 ,  C23C14/48 ,  C23C16/36 ,  C23C16/40 ,  C23C16/30 ,  C23C16/34

CPC classification number: C23C16/56 ,  C23C16/045 ,  C23C16/401

Abstract: Embodiments described herein relate to methods for forming flowable chemical vapor deposition (FCVD) films suitable for high aspect ratio gap fill applications. Various process flows described include ion implantation processes utilized to treat a deposited FCVD film to improve dielectric film density and material composition. Ion implantation processes, curing processes, and annealing processes may be utilized in various sequence combinations to form dielectric films having improved densities at temperatures within the thermal budget of device materials. Improved film quality characteristics include reduced film stress and reduced film shrinkage when compared to conventional FCVD film formation processes.

Abstract translation: 本文所述的实施方案涉及用于形成适用于高纵横比间隙填充应用的可流动化学气相沉积（FCVD）膜的方法。 所描述的各种工艺流程包括用于处理沉积的FCVD膜以改善电介质膜密度和材料组成的离子注入工艺。 离子注入工艺，固化过程和退火工艺可以以各种顺序组合使用，以在器件材料的热预算内的温度下形成具有改善的密度的电介质膜。 与常规的FCVD成膜方法相比，改进的膜质量特性包括膜应力减小和膜收缩减小。

公开(公告)号：US20150380526A1

公开(公告)日：2015-12-31

申请号：US14469241

申请日：2014-08-26

Applicant: Applied Materials, Inc.

Inventor： Ludovic GODET ,  Srinivas D. NEMANI ,  Jun XUE ,  Ellie Y. YIEH

IPC: H01L29/66 ,  H01L21/265 ,  H01L21/3205

CPC classification number: H01L29/66795 ,  H01J37/32357 ,  H01J2237/334 ,  H01L21/2236 ,  H01L21/26506 ,  H01L21/3065 ,  H01L29/66803 ,  H01L29/785

Abstract: Methods for forming fin structure with desired materials formed on different locations of the fin structure using an ion implantation process to define an etching stop layer followed by an etching process for manufacturing three dimensional (3D) stacking of fin field effect transistor (FinFET) for semiconductor chips are provided. In one embodiment, a method for forming a structure on a substrate includes performing an ion implantation process on a substrate having a plurality of structures formed thereon, forming an ion treated region in the structure at an interface between the ion treated region and an untreated region in the structure defining an etch stop layer, and performing a remote plasma etching process to etch the treated region from the substrate to exposed the untreated region.

Abstract translation: 使用离子注入工艺在翅片结构的不同位置形成所需材料的翅片结构的方法，以限定蚀刻停止层，随后进行用于制造用于半导体的鳍状场效应晶体管（FinFET）的三维（3D）堆叠的蚀刻工艺 提供芯片。 在一个实施例中，用于在衬底上形成结构的方法包括在其上形成有多个结构的衬底上执行离子注入工艺，在离子处理区域和未处理区域之间的界面处在该结构中形成离子处理区域 在限定蚀刻停止层的结构中，以及执行远程等离子体蚀刻工艺，以从基板蚀刻经处理的区域以暴露未处理区域。

公开(公告)号：US20150368801A1

公开(公告)日：2015-12-24

申请号：US14657405

申请日：2015-03-13

Applicant: Applied Materials, Inc.

Inventor： Jun XUE ,  Ludovic Godet ,  Qiwei Liang

IPC: C23C16/50 ,  C23C16/458 ,  C23C14/48 ,  H01J37/32

CPC classification number: C23C16/045 ,  H01J37/32357 ,  H01J37/32422 ,  H01J37/32449 ,  H01J37/32633

Abstract: Plasma process chambers employing distribution grids having focusing surfaces thereon enabling angled fluxes to reach a substrate, and associated methods are disclosed. A distribution grid is disposed in a chamber between the plasma and a substrate. The distribution grid includes a first surface facing the substrate and a focusing surface facing the plasma. A passageway extends through the distribution grid, and is sized with a width to prevent the plasma sheath from entering therein. By positioning the focusing surface at an angle other than parallel to the substrate, an ion flux from the plasma may be accelerated across the plasma sheath and particles of the flux pass through the passageway to be incident upon the substrate. In this manner, the angled ion flux may perform thin film deposition and etch processes on sidewalls of features extending orthogonally from or into the substrate, as well as angled implant and surface modification.

Abstract translation: 等离子体处理室采用其上具有聚焦表面的分配网格，其上形成有角度的焊剂以到达衬底，以及相关方法。 配电网布置在等离子体和基板之间的室中。 配电网包括面向衬底的第一表面和面向等离子体的聚焦表面。 通道延伸穿过配电网，并且具有宽度的尺寸以防止等离子体护套进入其中。 通过将聚焦表面定位在与衬底不同的角度处，来自等离子体的离子通量可以跨越等离子体鞘加速，并且助焊剂的颗粒通过通道入射到衬底上。 以这种方式，成角度的离子通量可以在从基底垂直延伸的特征的侧壁上进行薄膜沉积和蚀刻处理，以及成角度的植入物和表面改性。

公开(公告)号：US20160163546A1

公开(公告)日：2016-06-09

申请号：US14613545

申请日：2015-02-04

Applicant: Applied Materials, Inc.

Inventor： Ludovic GODET ,  Srinivas D. NEMANI ,  Erica CHEN ,  Jun XUE ,  Ellie Y. YIEH ,  Gary E. DICKERSON

IPC: H01L21/033 ,  H01L21/762 ,  H01L23/00 ,  H01L21/84

CPC classification number: H01L21/0337 ,  H01J2237/24528 ,  H01L21/0332 ,  H01L21/0335 ,  H01L21/3105 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/31155 ,  H01L21/32 ,  H01L21/76205 ,  H01L21/7624 ,  H01L21/823431 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/0924 ,  H01L27/10879 ,  H01L27/1211 ,  H01L29/66795 ,  H01L29/66803 ,  H01L29/7831

Abstract: Embodiments of the present disclosure relate to precision material modification of three dimensional (3D) features or advanced processing techniques. Directional ion implantation methods are utilized to selectively modify desired regions of a material layer to improve etch characteristics of the modified material. For example, a modified region of a material layer may exhibit improved etch selectivity relative to an unmodified region of the material layer. Methods described herein are useful for manufacturing 3D hardmasks which may be advantageously utilized in various integration schemes, such as fin isolation and gate-all-around, among others. Multiple directional ion implantation processes may also be utilized to form dopant gradient profiles within a modified layer to further influence etching processes.

Abstract translation: 本公开的实施例涉及三维（3D）特征或高级处理技术的精密材料修改。 方向离子注入方法用于选择性地修饰材料层的所需区域以改善改性材料的蚀刻特性。 例如，材料层的改性区域相对于材料层的未改性区域可以表现出改进的蚀刻选择性。 本文描述的方法可用于制造3D硬掩模，其可以有利地用于各种集成方案中，例如翅片隔离和门全部等。 多方向离子注入工艺也可用于在改性层内形成掺杂剂梯度分布，以进一步影响蚀刻工艺。

公开(公告)号：US20150315707A1

公开(公告)日：2015-11-05

申请号：US14267865

申请日：2014-05-01

Applicant: Applied Materials, Inc.

Inventor： Jun XUE ,  Jingjing LIU ,  Yongmei CHEN ,  Ludovic GODET ,  Chentsau YING ,  Shambhu N. ROY

IPC: C23C16/56 ,  C23C16/505 ,  C23C16/455 ,  C23C16/27 ,  C23C16/46

CPC classification number: C23C16/56 ,  C23C16/27 ,  C23C16/272 ,  C23C16/452 ,  C23C16/45523 ,  C23C16/45557 ,  C23C16/46 ,  C23C16/505

Abstract: Methods for making a nanocrystalline diamond layer are disclosed herein. A method of forming a layer can include activating a deposition gas comprising an alkane and a hydrogen containing gas at a first pressure, delivering the activated deposition gas to the substrate at a second pressure which is less than the first pressure, forming a nanocrystalline diamond layer, treating the layer with an activated hydrogen containing gas to remove one or more polymers from the surface and repeating the cycle to achieve a desired thickness.

Abstract translation: 本文公开了制备纳米晶体金刚石层的方法。 形成层的方法可以包括在第一压力下激活包括烷烃和含氢气体的沉积气体，在小于第一压力的第二压力下将活化的沉积气体输送到衬底，形成纳米晶体金刚石层 用活化的含氢气体处理层以从表面去除一种或多种聚合物并重复该循环以达到所需的厚度。