公开(公告)号：US09323657B1

公开(公告)日：2016-04-26

申请号：US14594934

申请日：2015-01-12

Applicant: SanDisk Technologies Inc.

Inventor： Rotem Sela ,  Eliad Adi Klein ,  Miki Sapir

IPC: G06F12/02

CPC classification number: G06F11/073 ,  G06F11/0793 ,  G06F2212/1024

Abstract: A memory system and method for improving read latency of a high-priority partition are provided. In one embodiment, a memory system receives a command to store data in the memory. The memory system determines if the command specified that the data is to be stored in a standard partition in the memory or in a high-priority partition in the memory. If the command specified that the data is to be stored in a standard partition in the memory, the memory system stores the data using a first write technique. If the command specified that the data is to be stored in a high-priority partition in the memory, the memory system stores the data using a second write technique, wherein the second write technique provides improved read latency of the stored data. Other embodiments are disclosed.

Abstract translation: 提供了一种用于提高高优先级分区的读延迟的存储器系统和方法。 在一个实施例中，存储器系统接收将数据存储在存储器中的命令。 存储器系统确定命令是否将数据存储在存储器中的标准分区中或存储器中的高优先级分区中。 如果命令指定将数据存储在存储器中的标准分区中，则存储器系统使用第一写入技术存储数据。 如果命令指定数据要存储在存储器中的高优先级分区中，则存储器系统使用第二写入技术来存储数据，其中第二写入技术提供所存储数据的改进的读延迟。 公开了其他实施例。

公开(公告)号：US20160111164A1

公开(公告)日：2016-04-21

申请号：US14518340

申请日：2014-10-20

Applicant: SANDISK TECHNOLOGIES INC.

Inventor： Hong-Yan Chen ,  Yingda Dong ,  Ching-Huang Lu

IPC: G11C16/14 ,  G11C16/04

CPC classification number: G11C16/14 ,  G11C11/5671 ,  G11C16/0466 ,  G11C16/0483 ,  G11C16/3404 ,  G11C16/3409 ,  G11C16/3413

Abstract: Techniques are provided to improve long term data retention in a charge-trapping memory device. In addition to a primary charge-trapping layer in which most charges are stored, the memory device may include a tunneling layer comprising an engineered tunneling barrier such as oxide-nitride-oxide. The nitride in the tunneling layer may also store some charges after programming. After the programming, a data retention operation is performed which de-traps some electrons from the tunneling layer, in addition to injecting holes into the tunneling layer which form neutral electron-hole dipoles in place of electrons. These mechanisms tend to lower threshold voltage. Additionally, the data retention operation redistributes the electrons and the holes inside the charge-trapping layer, resulting in an increase in threshold voltage which roughly cancels out the decrease when the data retention operation is optimized.

Abstract translation: 提供技术来改善电荷俘获存储器件中的长期数据保持。 除了存储大多数电荷的主电荷捕获层之外，存储器件可以包括隧道层，其包括工程化隧道势垒，例如氧化物 - 氮化物 - 氧化物。 在编程之后，隧道层中的氮化物也可能存储一些电荷。 在编程之后，除了将空穴注入到形成中性电子 - 空穴偶极子的隧道层中以代替电子之外，还执行了从隧道层去除一些电子的数据保留操作。 这些机制倾向于降低阈值电压。 此外，数据保持操作将电荷和空穴重新分布在电荷俘获层内部，导致阈值电压的增加，这在数据保持操作优化时大致抵消了减少。

公开(公告)号：US09318210B1

公开(公告)日：2016-04-19

申请号：US14611997

申请日：2015-02-02

Applicant: SanDisk Technologies, Inc.

Inventor： James V. Hart ,  Kenneth Louie ,  Khanh Nguyen ,  Man Mui

IPC: G11C11/34 ,  G11C16/04 ,  G11C16/26 ,  G11C16/08 ,  G11C16/34

CPC classification number: G11C16/26 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/3459 ,  G11C2211/5621

Abstract: When applying a sensing voltage at one end of a word line of a non-volatile memory circuit, an initial kick, where the voltage is initially raised somewhat above its final desired voltage, is used. Using on-chip circuitry for the determination of the RC time constant of the word lines allows for this kick to be trimmed to the specifics of the circuit. To further improve settling times for read operations is NAND type architectures, when raising the voltage to the desired read level on a selected word line, a reverse kick, where the non-selected word line's voltage is dropped briefly, can be applied to neighboring non-selected word lines.

Abstract translation: 当在非易失性存储器电路的字线的一端应用感测电压时，使用其中电压最初升高到其最终期望电压以上的初始踢脚。 使用片上电路来确定字线的RC时间常数允许将该脚趾修剪到电路的细节。 为了进一步提高读操作的建立时间，NAND型架构在将选定字线上的电压提高到期望的读取电平时，可以将未选择的字线的电压短暂地下降的反向跳转应用于相邻的非线性 - 选择的字线。

公开(公告)号：US09318204B1

公开(公告)日：2016-04-19

申请号：US14508352

申请日：2014-10-07

Applicant: SanDisk Technologies, Inc.

Inventor： Han Chen ,  Man Lung Mui ,  Kou Tei

IPC: G11C16/04 ,  G11C16/10 ,  G11C16/32

CPC classification number: G11C16/10 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/32 ,  G11C2211/5622 ,  G11C2216/14

Abstract: A non-volatile memory and method have programming circuitry that outputs a series of programming pulses of increasing voltage level to program in parallel a group of memory cells associated with a selected word line. Individual timing of the programming pulses such as rise and fall times of the pulse is optimally and dynamically adjusted according to the relative numbers of program-enabled and program-inhibited memory cells in the group associated with that pulse.

Abstract translation: 非易失性存储器和方法具有编程电路，其输出一系列具有增加的电压电平的编程脉冲以并行编程与所选字线相关联的一组存储器单元。 编程脉冲的单个定时（如脉冲的上升和下降时间）根据与脉冲相关联的组中的编程使能和程序禁止的存储器单元的相对数量被最佳和动态地调整。

公开(公告)号：US09318166B2

公开(公告)日：2016-04-19

申请号：US13329788

申请日：2011-12-19

Applicant: Eran Sharon ,  Idan Alrod

Inventor： Eran Sharon ,  Idan Alrod

IPC: G11C29/00 ,  G11C7/10 ,  G06F11/10 ,  G11C11/56 ,  G11C16/04 ,  G11C16/10

CPC classification number: G11C7/1006 ,  G06F11/1044 ,  G06F11/1068 ,  G06F11/1072 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/10 ,  G11C29/78 ,  G11C2211/5641

Abstract: A method of reading data in a data storage device with a controller and a memory includes generating, in the memory, a set of bits corresponding to a particular storage element of the memory. The set of bits indicates a group of threshold voltage intervals. A threshold voltage of the particular storage element corresponds to one of the threshold voltage intervals within the group. At least one threshold voltage interval within the group is separated from another threshold voltage interval within the group by an intervening threshold voltage interval that is not within the group. The method also includes sending the set of bits to the controller. The set of bits includes a first hard bit that corresponds to a value read from the particular storage element and a first soft bit that corresponds to a reliability measure.

Abstract translation: 利用控制器和存储器在数据存储装置中读取数据的方法包括在存储器中生成与存储器的特定存储元件相对应的一组位。 这组位指示一组阈值电压间隔。 特定存储元件的阈值电压对应于组内的阈值电压间隔之一。 组内的至少一个阈值电压间隔与组内的另一个阈值电压间隔分开，不在组内的中间阈值电压间隔。 该方法还包括将该组位发送到控制器。 所述位组包括对应于从特定存储元件读取的值的第一硬比特和对应于可靠性度量的第一软比特。

公开(公告)号：US09312026B2

公开(公告)日：2016-04-12

申请号：US14466786

申请日：2014-08-22

Applicant: SanDisk Technologies Inc.

Inventor： Mrinal Kochar ,  Gautam Dusija ,  Chris Avila ,  Yingda Dong ,  Man Mui ,  Yichao Huang ,  Deepak Raghu

IPC: G11C16/16 ,  G11C16/34

CPC classification number: G11C16/3445 ,  G11C16/0483 ,  G11C16/16 ,  G11C2216/18 ,  H01L27/11556 ,  H01L27/11582

Abstract: In a three-dimensional nonvolatile memory, when a block erase failure occurs, zones within a block may be separately verified to see if some zones pass verification. Zones that pass may be designated as good zones and may subsequently be used to store user data while bad zones in the same block may be designated as bad and may not be used for subsequent storage of user data.

Abstract translation: 在三维非易失性存储器中，当发生块擦除故障时，块内的区域可以单独验证，以查看某些区域是否通过验证。 通过的区域可以被指定为良好区域，并且可以随后用于存储用户数据，同一块中的不良区域可能被指定为不良，并且可能不用于用户数据的后续存储。

公开(公告)号：US09312015B1

公开(公告)日：2016-04-12

申请号：US14523848

申请日：2014-10-25

Applicant: SANDISK TECHNOLOGIES INC.

Inventor： Chia-Lin Hsiung ,  Fumiaki Toyama ,  Masaaki Higashitani

IPC: G11C16/04 ,  G11C16/24

CPC classification number: G11C16/10 ,  G11C8/08 ,  G11C16/08 ,  G11C16/12 ,  H01L27/0207 ,  H01L27/11529

Abstract: Methods for reducing an increase in the threshold voltage of a transistor due to the body effect and increasing the junction breakdown voltage for junctions of the transistor are described. The transistor may comprise an NMOS transistor that transfers a programming voltage (e.g., 24V) to a word line of a memory array during a programming operation. In some cases, a first poly shield may be positioned within a first distance of a gate of the transistor and may comprise a first polysilicon structure that is directly adjacent to the gate of the transistor. The first poly shield may be arranged in a first direction (e.g., in the channel length direction of the transistor). The first poly shield may be biased to a first voltage greater than ground (e.g., 10V) during the programming operation to reduce an increase in the threshold voltage of the transistor due to the body effect.

Abstract translation: 描述了用于减小由于体效应引起的晶体管阈值电压增加并增加晶体管结的结击穿电压的方法。 晶体管可以包括在编程操作期间将编程电压（例如，24V）传送到存储器阵列的字线的NMOS晶体管。 在一些情况下，第一多晶硅屏蔽可以位于晶体管的栅极的第一距离内，并且可以包括与晶体管的栅极直接相邻的第一多晶硅结构。 第一多晶硅屏蔽可以沿第一方向（例如，在晶体管的沟道长度方向）上布置。 在编程操作期间，第一多晶屏蔽可被偏压到大于接地（例如10V）的第一电压，以减少由于身体效应引起的晶体管的阈值电压的增加。

公开(公告)号：US09311970B2

公开(公告)日：2016-04-12

申请号：US14495425

申请日：2014-09-24

Applicant: SANDISK TECHNOLOGIES INC.

Inventor： Eran Sharon ,  Idan Alrod ,  Simon Litsyn

IPC: G11C29/00 ,  G11C7/10 ,  G06F11/10 ,  G11C11/56 ,  G11C16/04 ,  G11C16/10

CPC classification number: G11C7/1006 ,  G06F11/1044 ,  G06F11/1068 ,  G06F11/1072 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/10 ,  G11C29/78 ,  G11C2211/5641

Abstract: A method of writing data includes receiving a data page to be stored in a data storage device and initiating an encode operation to encode the data page. The encode operation generates first encoded data and a first portion of the first encoded data is stored to the first physical page of the data storage device. The method includes initiating storage of a second portion of the first encoded data to a second physical page of the data storage device. The method also includes initiating a decode operation to recover the data page. The decode operation uses a representation of the first portion of the first encoded data that is read from the first physical page without using any data from the second physical page.

Abstract translation: 一种写入数据的方法包括：接收要存储在数据存储设备中的数据页，并启动对数据页进行编码的编码操作。 编码操作生成第一编码数据，并且第一编码数据的第一部分被存储到数据存储设备的第一物理页面。 该方法包括启动第一编码数据的第二部分的存储到数据存储设备的第二物理页面。 该方法还包括启动解码操作以恢复数据页面。 解码操作使用从第一物理页读取的第一编码数据的第一部分的表示，而不使用来自第二物理页的任何数据。

公开(公告)号：US20160098215A1

公开(公告)日：2016-04-07

申请号：US14506147

申请日：2014-10-03

Applicant: SanDisk Technologies, Inc.

Inventor： Yiwei Song ,  Xinde Hu ,  Daniel Tuers

IPC: G06F3/06

CPC classification number: G06F3/0619 ,  G06F3/064 ,  G06F3/0653 ,  G06F3/0679 ,  G06F12/0246 ,  G06F12/0646 ,  G06F2212/7201 ,  G06F2212/7202 ,  G06F2212/7206 ,  G06F2212/7207

Abstract: Systems, apparatuses, and methods are provided that dynamically reassign counters (or other memory monitors) in a memory. A plurality of counters may be assigned to different address ranges within an overall address range of a memory. The value of the counter may be indicative of activity, such as reads, within a respective assigned address range. Depending on the value of the counter, the respective address range of the counter may be dynamically changed. For example, a counter with a high value (indicating higher activity within the address range) may have its respective address range divided, with two counters being assigned to each of the divided address ranges. Likewise, counters with low values (indicating less activity within the address ranges) may have their respective address ranges combined, with a single counter being assigned to the combined address ranges. Thus, in subdividing and combining address ranges, the number of counters assigned may remain the same, while still monitoring the activity with the overall address range.

Abstract translation: 提供了在存储器中动态重新分配计数器（或其他存储器监视器）的系统，装置和方法。 可以将多个计数器分配给存储器的整个地址范围内的不同地址范围。 计数器的值可以指示在相应的分配的地址范围内的活动，例如读取。 根据计数器的值，可以动态地改变计数器的相应地址范围。 例如，具有高值的计数器（指示地址范围内的更高的活动度）可以将其各自的地址范围划分，其中两个计数器被分配给每个划分的地址范围。 类似地，具有低值的计数器（在地址范围内指示较少的活动）可以具有其各自的地址范围的组合，其中单个计数器被分配给组合的地址范围。 因此，在细分和组合地址范围时，分配的计数器数量可能保持不变，同时仍然以整体地址范围监视活动。

公开(公告)号：US20160092302A1

公开(公告)日：2016-03-31

申请号：US14700543

申请日：2015-04-30

Applicant: SanDisk Technologies Inc.

Inventor： Dinesh Agarwal ,  Vijay Sivasankaran

IPC: G06F11/10 ,  G06F3/06 ,  G11C29/52

CPC classification number: G06F11/1068 ,  G06F3/0616 ,  G06F3/0619 ,  G06F3/064 ,  G06F3/0679 ,  G11C7/20 ,  G11C29/52

Abstract: A memory system or flash memory device may include mechanism for handling power loss with a dual programming architecture. The state of primary and secondary blocks may be reconstructed to a state immediately preceding a power loss. The reconstruction may include comparing error correction code (ECC) headers of blocks to recreate a block exchange with fewer control updates. The comparison can be used to identify a primary and secondary block. The header may identify a particular stream, identify a free block, identify a release block, and other information.

Abstract translation: 存储器系统或闪存设备可以包括用于利用双重编程架构来处理功率损耗的机制。 主和次级块的状态可以被重建为紧接在功率损耗之前的状态。 重建可以包括比较块的纠错码（ECC）头部，以用更少的控制更新来重建块交换。 比较可用于识别主要和次要块。 标题可以标识特定流，标识空闲块，识别释放块和其他信息。