公开(公告)号：US12119073B2

公开(公告)日：2024-10-15

申请号：US17883607

申请日：2022-08-09

申请人： ASPEED Technology Inc.

发明人： Hung-Ming Lin ,  Hung-Ju Huang

IPC分类号： G11C29/52 ,  G06F7/58 ,  G11C7/10 ,  G11C29/02

CPC分类号： G11C29/52 ,  G06F7/58 ,  G11C7/1039 ,  G11C29/022

摘要： The disclosure provides an integrated circuit and an operation method and an inspection method thereof. The integrated circuit includes a one-time programmable (OTP) memory, an identifier generation circuit, and a memory controller. The identifier generation circuit generates a random number, and performs an error-detection-code encoding operation on the random number to generate an identifier with an error-detection code. The memory controller writes the identifier generated by the identifier generation circuit into the OTP memory. The identifier generation circuit reads the identifier from the OTP memory through the memory controller, and performs an error-detection-code decoding operation on the identifier provided by the memory controller to determine whether an error of the identifier from the OTP memory is correctable. When it is determined that the error of the identifier from the OTP memory is not correctable, the writing of the identifier is deemed failed.

公开(公告)号：US12119059B2

公开(公告)日：2024-10-15

申请号：US17990723

申请日：2022-11-20

申请人： COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES ,  WEEBIT NANO LTD

发明人： Bastien Giraud ,  Cyrille Laffond ,  Sebastien Ricavy ,  Valentin Gherman ,  Ilan Sever

IPC分类号： G11C13/00 ,  G11C29/52

CPC分类号： G11C13/0069 ,  G11C13/004 ,  G11C29/52

摘要： A method is provided for writing a data word to a resistive memory consisting of 2T2R differential cells each having first and second sets of a resistor (R) and a selection transistor (T). The method includes generating an initial codeword, programming it in 1T1R mode, checking its programming in 1T1R mode, inverting it, programming the inverted initial codeword in 1T1R mode, checking its programming in 1T1R mode, and reading, in 2T2R differential mode, that the read data correspond to said initial data. A device designed to implement this write method and to an electronic system including this device is also provided.

公开(公告)号：US20240339171A1

公开(公告)日：2024-10-10

申请号：US18490685

申请日：2023-10-19

申请人： SK hynix Inc.

发明人： Dong Sop LEE ,  Tae Ho LIM

IPC分类号： G11C29/52 ,  H03M13/00 ,  H03M13/11

CPC分类号： G11C29/52 ,  H03M13/11 ,  H03M13/611

摘要： A phase-change memory controller controls a phase-change memory device. The phase-change memory controller includes a write control circuit configured to receive first write data of “N” bits (where “N” is a natural number greater than 2) to be written to the phase-change memory device to generate second write data composed of compressed data compressed with “M” bits (where “N” is a natural number smaller than “N”) and “0” padding data in which the rest “N-M” bits are filled with “0”.

公开(公告)号：US12112822B2

公开(公告)日：2024-10-08

申请号：US17903052

申请日：2022-09-06

申请人： Winbond Electronics Corp.

发明人： Chih-Feng Lin

IPC分类号： G11C29/00 ,  G11C29/52

CPC分类号： G11C29/52 ,  G11C29/781 ,  G11C29/785

摘要： A multi-channel memory device includes N first memory blocks, a first redundancy memory block, and N first interface circuits. Each of the first interface circuits is coupled to two of the first memory blocks and the first redundancy memory block. The first interface circuits respectively select N first selected memory blocks in the first memory block and the first redundancy memory block according to a plurality of first selection signals, where N is a positive integer greater than 1.

公开(公告)号：US12112809B2

公开(公告)日：2024-10-08

申请号：US18219083

申请日：2023-07-06

申请人： Silicon Motion, Inc.

发明人： Tsung-Chieh Yang

IPC分类号： G06F11/10 ,  G06F3/06 ,  G06F11/07 ,  G06F11/30 ,  G06F13/16 ,  G06F13/28 ,  G11C11/56 ,  G11C16/04 ,  G11C16/26 ,  G11C16/34 ,  G11C29/52 ,  H03M13/15

CPC分类号： G11C16/26 ,  G06F3/0619 ,  G06F3/064 ,  G06F3/0659 ,  G06F3/0679 ,  G06F11/1068 ,  G06F11/1072 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/3427 ,  G11C29/52 ,  H03M13/152 ,  G11C16/0475 ,  G11C2211/5644 ,  G11C2211/5648

摘要： A method for reading data stored in a flash memory includes at least the following steps: controlling the flash memory to perform a plurality of read operations upon a plurality of memory cells included in the flash memory; obtaining a plurality of bit sequences read from the memory cells, respectively, wherein the read operations read bits of a predetermined bit order from the memory cells by utilizing different control gate voltage settings; and determining readout information of the memory cells according to binary digit distribution characteristics of the bit sequences.

公开(公告)号：US20240322845A1

公开(公告)日：2024-09-26

申请号：US18680900

申请日：2024-05-31

申请人： KIOXIA CORPORATION

发明人： Riki SUZUKI ,  Toshikatsu HIDA ,  Osamu TORII ,  Hiroshi YAO ,  Kiyotaka IWASAKI

IPC分类号： H03M13/35 ,  G06F3/06 ,  G06F11/10 ,  G11B20/18 ,  G11C7/10 ,  G11C29/04 ,  G11C29/52 ,  H03M13/29

CPC分类号： H03M13/35 ,  G06F3/0619 ,  G06F3/064 ,  G06F3/0653 ,  G06F3/0679 ,  G06F11/1008 ,  G06F11/1044 ,  G06F11/1048 ,  G06F11/1068 ,  G06F11/1076 ,  G11C29/52 ,  H03M13/29 ,  H03M13/2906 ,  H03M13/2957 ,  G11B20/1833 ,  G11C7/1006 ,  G11C2029/0411

摘要： According to one embodiment, a nonvolatile memory includes a plurality of memory areas and controller circuit including an error correction code encoder. The error correction code encoder encodes a first data to generate a first parity in a first operation and encodes a second data to generate a second parity in a second operation. The controller circuit writes the first data and the first parity into a first memory area among the plurality of memory areas and writes the second data and the second parity into a second memory area among the plurality of memory areas. The size of the second data is smaller than the size of the first data and the size of the second parity is equal to the size of the first parity.

公开(公告)号：US12101379B2

公开(公告)日：2024-09-24

申请号：US18312435

申请日：2023-05-04

申请人： PURE STORAGE, INC.

发明人： Prabhath Sajeepa ,  Daniel Talayco ,  Qing Yang ,  Robert Lee

IPC分类号： G06F12/00 ,  G06F3/06 ,  G06F11/10 ,  G06F11/20 ,  G06F12/02 ,  G11C29/52 ,  H03M13/15 ,  H04L49/10 ,  H04L67/1097 ,  H04L67/51

CPC分类号： H04L67/1097 ,  G06F3/06 ,  G06F3/0604 ,  G06F3/061 ,  G06F3/0611 ,  G06F3/0613 ,  G06F3/0635 ,  G06F3/065 ,  G06F3/0655 ,  G06F3/0659 ,  G06F3/067 ,  G06F3/0685 ,  G06F3/0688 ,  G06F3/0689 ,  G06F11/1068 ,  G06F11/2092 ,  G06F12/0246 ,  G11C29/52 ,  H03M13/154 ,  H04L49/10 ,  H04L67/51 ,  G06F11/108 ,  G06F2201/805 ,  G06F2201/845 ,  G06F2212/7206 ,  G06F2212/7207

摘要： A storage system is provided. The storage system includes a first storage cluster, the first storage cluster having a first plurality of storage nodes coupled together and a second storage cluster, the second storage cluster having a second plurality of storage nodes coupled together. The system includes an interconnect coupling the first storage cluster and the second storage cluster and a first pathway coupling the interconnect to each storage cluster. The system includes a second pathway, the second pathway coupling at least one fabric module within a chassis to each blade within the chassis.

公开(公告)号：US20240312554A1

公开(公告)日：2024-09-19

申请号：US18600360

申请日：2024-03-08

申请人： Micron Technology, Inc.

发明人： Chun Sum Yeung ,  Deping He ,  Zhongyuan Lu

IPC分类号： G11C29/52 ,  G11C11/406 ,  G11C29/02

CPC分类号： G11C29/52 ,  G11C11/40622 ,  G11C29/022

摘要： Methods, systems, and devices for efficient read disturb scanning are described. A memory system may limit a quantity of word lines scanned as part of a read disturb scan. For example, the memory system may select a threshold quantity of word lines of a block for the read disturb scan based on a characterization of the word lines, such as selecting one or more word lines having higher bit error rates than other word lines of the block. The memory system may perform the read disturb scan on the selected one or more word lines to determine respective failure bit counts of the selected word lines and exclude unselected word lines of the block from the read disturb scan. The memory system may determine whether to perform a refresh operation on the block based on whether a respective failure bit count satisfies a threshold failure bit count.

公开(公告)号：US12094541B2

公开(公告)日：2024-09-17

申请号：US17452463

申请日：2021-10-27

申请人： Kioxia Corporation

发明人： Tsukasa Tokutomi ,  Masanobu Shirakawa ,  Kengo Kurose ,  Marie Takada ,  Ryo Yamaki ,  Kiyotaka Iwasaki ,  Yoshihisa Kojima

IPC分类号： G11C7/00 ,  G06F3/06 ,  G06F11/10 ,  G11C11/56 ,  G11C16/04 ,  G11C16/26 ,  G11C29/52 ,  G11C16/08 ,  H10B43/27 ,  H10B43/35

CPC分类号： G11C16/26 ,  G06F3/0604 ,  G06F3/0659 ,  G06F3/0679 ,  G06F11/1068 ,  G11C11/5671 ,  G11C16/0483 ,  G11C29/52 ,  G11C16/08 ,  H10B43/27 ,  H10B43/35

摘要： According to one embodiment, a memory system includes a nonvolatile memory and a memory controller. The memory controller is configured: to store, in a buffer, a data set read from a cell unit, and an expected data set generated by an error correction on the data set; to count a number of first and second memory cells corresponding to a first and a second combination of data in the data set and the expected data set, respectively, among the memory cells in the cell unit; to calculate a shift amount of a read voltage used in a read operation from the cell unit, based on the number of the first and second memory cells; and to apply the shift amount to a next read operation from the first cell unit.

公开(公告)号：US20240303158A1

公开(公告)日：2024-09-12

申请号：US18604227

申请日：2024-03-13

申请人： Micron Technology, Inc.

发明人： Scott E. Schaefer ,  Aaron P. Boehm

IPC分类号： G06F11/10 ,  G06F3/06 ,  G06F11/20 ,  G06F13/00 ,  G11C7/10 ,  G11C11/22 ,  G11C11/4093 ,  G11C29/52 ,  H03M13/00 ,  H03M13/19 ,  H03M13/45

CPC分类号： G06F11/1068 ,  G11C11/221 ,  G11C11/2273 ,  G11C11/2275 ,  H03M13/458 ,  G06F3/0659 ,  G06F11/1052 ,  G06F11/201 ,  G06F13/00 ,  G11C7/1006 ,  G11C11/4093 ,  G11C29/52 ,  H03M13/19 ,  H03M13/6561

摘要： Methods, systems, and devices for a memory device with an error correction memory device with fast data access are described. For example, during a read operation, a memory device may be configured to output the data indicated by the read operation concurrent with performing an error correction operation. If the memory device detects an error, the memory device may indicate the error to a host device and, in some cases, output the corrected data to the host device. During a write operation, the memory device may store error detection or correction information associated with data to be stored at the memory device. The memory device may, in some cases, store error detection or correction information generated by the host device.