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    STORAGE CONTROLLER AND METHOD OF OPERATING ELECTRONIC SYSTEM
    1.
    发明公开
    STORAGE CONTROLLER AND METHOD OF OPERATING ELECTRONIC SYSTEM 审中-公开

    公开(公告)号：US20230179418A1

    公开(公告)日：2023-06-08

    申请号：US17898045

    申请日：2022-08-29

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Kyungwoo Noh ,  Jisoo Kim ,  Kyungjin Lee ,  Younghyun Ji

    IPC: H04L9/32 ,  H04L9/06 ,  H04L9/08

    CPC classification number: H04L9/3213 ,  H04L9/0643 ,  H04L9/0861 ,  H04L9/3247

    Abstract: A storage device includes a memory device storing data, and a controller controlling the memory device. The controller obtains and stores a certificate including a public key of an administrator from a host device, provides a nonce to the host device in response to a request from the host device, receives a token request signature including the nonce, a user identifier (ID), an allowed command list and a lifetime from the host device, and when it is verified that the token request signature is generated by a legitimate administrator by decrypting the token request signature with the public key, generates a token for allowing a user corresponding to the user ID to execute a command included in the allowed command list during the lifetime, and a token secret key corresponding to the token, and provides the token and the token secret key to the host device.

    FRACTIONAL DIVIDER WITH PHASE SHIFTER AND FRACTIONAL PHASE LOCKED LOOP INCLUDING THE SAME
    2.
    发明公开
    FRACTIONAL DIVIDER WITH PHASE SHIFTER AND FRACTIONAL PHASE LOCKED LOOP INCLUDING THE SAME 审中-公开

    公开(公告)号：US20230170912A1

    公开(公告)日：2023-06-01

    申请号：US17964377

    申请日：2022-10-12

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Baekmin LIM ,  Seungjin KIM ,  Seunghyun OH

    IPC: H03L7/197 ,  H03L7/081 ,  H03L7/093

    CPC classification number: H03L7/1976 ,  H03L7/081 ,  H03L7/093

    Abstract: A fractional divider processing circuitry is to receive one of a plurality of clock signals as an input clock signal, and generate a first division clock signal based on the input clock signal and a first control signal. Phases of the plurality of clock signals partially overlap each other. The processing circuitry generates a delta-sigma modulation signal based on the first division clock signal and a frequency control word, and generates a second division clock signal based on the plurality of clock signals, the first division clock signal and a second control signal. The second control signal corresponds to a quantization noise of the delta-sigma modulation signal. The processing circuitry generates the second control signal and a digital control word based on the quantization noise of the delta-sigma modulator. The processing circuitry generates a final division clock signal based on the second division clock signal and the digital control word.

    SEMICONDUCTOR MEMORY DEVICES
    3.
    发明公开
    SEMICONDUCTOR MEMORY DEVICES 审中-公开

    公开(公告)号：US20230200053A1

    公开(公告)日：2023-06-22

    申请号：US17945235

    申请日：2022-09-15

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Yangdoo Kim ,  Yonghwan Kim ,  Sangwuk Park ,  Sunghyun Park ,  Jinyoung Park ,  Minkyu Suh ,  Jungpyo Hong

    IPC: H10B12/00

    CPC classification number: H10B12/315 ,  H10B12/34 ,  H10B12/033

    Abstract: A semiconductor memory device includes a substrate including a memory cell region, a plurality of capacitor structures arranged in the memory cell region of the substrate and including a plurality of lower electrodes, a capacitor dielectric layer, and an upper electrode, a first support pattern contacting sidewalls of the plurality of lower electrodes of the plurality of capacitor structures to support the plurality of lower electrodes, and a second support pattern located at a higher vertical level than a vertical level of the first support pattern and contacting the sidewalls of the plurality of lower electrodes to support the plurality of lower electrodes. The plurality of lower electrodes have a plurality of recessed electrode portions, respectively, in upper portions of the plurality of lower electrodes.

    MAGNETORESISTIVE RANDOM ACCESS MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME
    4.
    发明申请
    MAGNETORESISTIVE RANDOM ACCESS MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME 有权

    公开(公告)号：US20250151629A1

    公开(公告)日：2025-05-08

    申请号：US18799264

    申请日：2024-08-09

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Hyungjong JEONG

    IPC: H10N50/10 ,  H01L23/528 ,  H10B61/00 ,  H10N50/01 ,  H10N50/80

    Abstract: A magnetoresistive random access memory device may include a wiring structure on a substrate, an etch stop layer on the wiring structure, an interlayer insulation layer on the etch stop layer, a plurality of contact structures penetrating the interlayer insulation layer and the etch stop layer to contact the wiring structure, each of the plurality of contact structures including a first portion having a sidewall facing the interlayer insulation layer and a second portion having a sidewall facing the etch stop layer, and a plurality of magnetic tunnel junction structures on the plurality of contact structures and connected to corresponding ones of the plurality of contact structures, respectively, wherein a first width of the first portion in a first horizontal direction is greater than a second width of the second portion in the first horizontal direction.

    IMAGE SENSOR
    7.
    发明申请
    IMAGE SENSOR 有权

    公开(公告)号：US20250151445A1

    公开(公告)日：2025-05-08

    申请号：US18742302

    申请日：2024-06-13

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Ingyu BAEK ,  Jinmyoung LEE ,  Soonhyung HONG

    IPC: H01L27/146

    Abstract: An image sensor that includes a first layer and a second layer bonded to the first layer. The first layer includes a first substrate including a first front surface and a first back surface, a floating diffusion region formed in the first substrate, a first pad, and a first conductive line provided between the floating diffusion region and the first pad. The second layer includes a second substrate including a second front surface and a second back surface, pixel transistors formed on the second substrate, a second pad, and a second conductive line provided between one of the pixel transistors and the second pad. The second conductive line passes through the second substrate and is electrically connected to a lower portion of the pixel transistor.

    METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
    9.
    发明申请
    METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE 有权

    公开(公告)号：US20250151304A1

    公开(公告)日：2025-05-08

    申请号：US19009795

    申请日：2025-01-03

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Choongsun Kim ,  Shigenobu Maeda ,  Myoungkyu Park

    IPC: H10D30/01 ,  H10D30/62 ,  H10D84/01 ,  H10D84/03

    Abstract: A method of manufacturing a semiconductor device includes forming an active fin protruding from a substrate and extending in a first direction; forming sacrificial gate patterns intersecting the active fin and extend in a second direction; forming recess regions by etching the active fin on at least one side of each of the sacrificial gate patterns; forming source/drain regions on the recess regions; removing the sacrificial gate patterns to form openings; and forming a gate dielectric layer and a gate electrode such that gate structures are formed to cover the active fin in the openings. The source/drain regions are formed by an epitaxial growth process and an in-situ doping process of doping first conductivity-type impurity elements. In at least one of the source/drain regions, after the in-situ doping process is performed, counter-doping is performed using second conductivity-type impurity elements different from the first conductivity-type impurity elements to decrease carrier concentration.

    MEMORY DEVICE HAVING COP STRUCTURE AND MEMORY PACKAGE INCLUDING THE SAME
    10.
    发明申请
    MEMORY DEVICE HAVING COP STRUCTURE AND MEMORY PACKAGE INCLUDING THE SAME 有权

    公开(公告)号：US20250151292A1

    公开(公告)日：2025-05-08

    申请号：US18732795

    申请日：2024-06-04

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Changyoung Lee ,  Keonwoo Park ,  Hyunchul Yoon

    IPC: H10B80/00 ,  G06F11/10 ,  G11C11/408 ,  G11C11/4091 ,  H01L23/00 ,  H01L25/065 ,  H01L25/18

    Abstract: A memory device includes a first semiconductor layer and a second semiconductor layer. The first semiconductor layer includes a memory cell array. The memory cell array is connected to a plurality of wordlines and a plurality of bitlines, and includes a plurality of normal memory cells storing normal data and a plurality of error correction code (ECC) memory cells storing ECC data. The second semiconductor layer is disposed with respect to the first semiconductor layer in a vertical direction, and includes a peripheral circuit. The peripheral circuit controls the memory cell array, and includes a row decoder. At least a portion of a region in which the plurality of ECC memory cells are disposed in the first semiconductor layer and at least a portion of a region in which the row decoder is disposed in the second semiconductor layer overlap in a plan view.

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