公开(公告)号：US20240087640A1

公开(公告)日：2024-03-14

申请号：US18143127

申请日：2023-05-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seongjin Cho ,  Kyuchang Kang ,  Keonwoo Park ,  Donghak Shin

IPC: G11C11/408 ,  G11C11/4091 ,  H01L25/065 ,  H10B12/00 ,  H10B80/00

CPC classification number: G11C11/4085 ,  G11C11/4087 ,  G11C11/4091 ,  H01L25/0655 ,  H10B12/482 ,  H10B12/488 ,  H10B12/50 ,  H10B80/00

Abstract: A semiconductor device includes a memory cell array that includes a plurality of memory cells electrically connected to a plurality of word lines and a plurality of bit lines, a word line driving circuit that includes a plurality of sub-word line decoders electrically connected to the plurality of word lines, and a control logic configured to determine a selected word line and unselected word lines among the plurality of word lines, and configured to control the word line driving circuit such that at least one of the unselected word lines that is adjacent to the selected word line is floated during at least a portion of a period in which a voltage of the selected word line returns to an initial level.

公开(公告)号：US20250151292A1

公开(公告)日：2025-05-08

申请号：US18732795

申请日：2024-06-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Changyoung Lee ,  Keonwoo Park ,  Hyunchul Yoon

IPC: H10B80/00 ,  G06F11/10 ,  G11C11/408 ,  G11C11/4091 ,  H01L23/00 ,  H01L25/065 ,  H01L25/18

Abstract: A memory device includes a first semiconductor layer and a second semiconductor layer. The first semiconductor layer includes a memory cell array. The memory cell array is connected to a plurality of wordlines and a plurality of bitlines, and includes a plurality of normal memory cells storing normal data and a plurality of error correction code (ECC) memory cells storing ECC data. The second semiconductor layer is disposed with respect to the first semiconductor layer in a vertical direction, and includes a peripheral circuit. The peripheral circuit controls the memory cell array, and includes a row decoder. At least a portion of a region in which the plurality of ECC memory cells are disposed in the first semiconductor layer and at least a portion of a region in which the row decoder is disposed in the second semiconductor layer overlap in a plan view.

公开(公告)号：US12236998B2

公开(公告)日：2025-02-25

申请号：US18143127

申请日：2023-05-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seongjin Cho ,  Kyuchang Kang ,  Keonwoo Park ,  Donghak Shin

IPC: G11C11/40 ,  G11C11/408 ,  G11C11/4091 ,  H01L25/065 ,  H10B12/00 ,  H10B80/00

Abstract: A semiconductor device includes a memory cell array that includes a plurality of memory cells electrically connected to a plurality of word lines and a plurality of bit lines, a word line driving circuit that includes a plurality of sub-word line decoders electrically connected to the plurality of word lines, and a control logic configured to determine a selected word line and unselected word lines among the plurality of word lines, and configured to control the word line driving circuit such that at least one of the unselected word lines that is adjacent to the selected word line is floated during at least a portion of a period in which a voltage of the selected word line returns to an initial level.