公开(公告)号：US20240096402A1

公开(公告)日：2024-03-21

申请号：US18240045

申请日：2023-08-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Changyoung Lee ,  Kyuchang Kang

IPC: G11C11/4091 ,  G11C11/4094

CPC classification number: G11C11/4091 ,  G11C11/4094

Abstract: A sense amplifier includes a first isolation transistor connected to a first memory cell through a first bit line, a second isolation transistor connected to a second memory cell through a second bit line, and sense amplifying circuitry connected to the first memory cell through the first isolation transistor, connected to the second memory cell through the second isolation transistor, and latch, to a pair of sense bit lines, data corresponding to a cell voltage stored in the first memory cell or the second memory cell, wherein the sense amplifying circuitry is configured to perform an offset cancellation operation while a charge sharing operation is performed between the first memory cell and the first bit line or between the second memory cell and the second bit line.

公开(公告)号：US20250040126A1

公开(公告)日：2025-01-30

申请号：US18670805

申请日：2024-05-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Taejin Kim ,  Taejin Park ,  Kyuchang Kang ,  Hyeonkyu Lee ,  Sungsoo Yim

IPC: H10B12/00

Abstract: A semiconductor device includes a lower circuit pattern, a bit line shield structure, a first insulating interlayer, a bit line structure, a first contact plug, a channel and a capacitor. The lower circuit pattern is on a substrate. The bit line shield structure is on the lower circuit pattern. The first insulating interlayer is in an opening extending through the bit line shield structure. The bit line structure is on the bit line shield structure, and at least partially overlaps the bit line shield structure in a vertical direction substantially perpendicular to an upper surface of the substrate. The first contact plug extends through the first insulating interlayer to contact the bit line structure, and is electrically connected to the lower circuit pattern. The channel is on the bit line structure. The capacitor is on the channel and is electrically connected to the channel.

公开(公告)号：US12236998B2

公开(公告)日：2025-02-25

申请号：US18143127

申请日：2023-05-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seongjin Cho ,  Kyuchang Kang ,  Keonwoo Park ,  Donghak Shin

IPC: G11C11/40 ,  G11C11/408 ,  G11C11/4091 ,  H01L25/065 ,  H10B12/00 ,  H10B80/00

Abstract: A semiconductor device includes a memory cell array that includes a plurality of memory cells electrically connected to a plurality of word lines and a plurality of bit lines, a word line driving circuit that includes a plurality of sub-word line decoders electrically connected to the plurality of word lines, and a control logic configured to determine a selected word line and unselected word lines among the plurality of word lines, and configured to control the word line driving circuit such that at least one of the unselected word lines that is adjacent to the selected word line is floated during at least a portion of a period in which a voltage of the selected word line returns to an initial level.

公开(公告)号：US20250149080A1

公开(公告)日：2025-05-08

申请号：US18784796

申请日：2024-07-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junhee Cho ,  Incheol Nam ,  Kyuchang Kang ,  Sangyun Kim ,  Sunyoung Kim ,  Jongwook Park ,  Hoseok Lee ,  Kangsub Jeong

IPC: G11C11/4091 ,  G11C11/4094

Abstract: A memory device includes a memory cell array, a sense amplifier, a voltage generation circuit and a control circuit. The memory cell array includes a plurality of bit lines to which a plurality of memory cells are connected, and a shielding bit line arranged between the plurality of bit lines and on lower portions of the plurality of bit lines. The sense amplifier is configured to sense and amplify data stored in a memory cell selected from among the plurality of memory cells. The voltage generation circuit is configured to generate a bit line precharge voltage and an internal power voltage based on a power voltage of the memory device. The control circuit is configured to selectively provide the shielding bit line with the bit line precharge voltage or the internal power voltage.

公开(公告)号：US20240087640A1

公开(公告)日：2024-03-14

申请号：US18143127

申请日：2023-05-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seongjin Cho ,  Kyuchang Kang ,  Keonwoo Park ,  Donghak Shin

IPC: G11C11/408 ,  G11C11/4091 ,  H01L25/065 ,  H10B12/00 ,  H10B80/00

CPC classification number: G11C11/4085 ,  G11C11/4087 ,  G11C11/4091 ,  H01L25/0655 ,  H10B12/482 ,  H10B12/488 ,  H10B12/50 ,  H10B80/00

Abstract: A semiconductor device includes a memory cell array that includes a plurality of memory cells electrically connected to a plurality of word lines and a plurality of bit lines, a word line driving circuit that includes a plurality of sub-word line decoders electrically connected to the plurality of word lines, and a control logic configured to determine a selected word line and unselected word lines among the plurality of word lines, and configured to control the word line driving circuit such that at least one of the unselected word lines that is adjacent to the selected word line is floated during at least a portion of a period in which a voltage of the selected word line returns to an initial level.