公开(公告)号：US12051461B2

公开(公告)日：2024-07-30

申请号：US17748357

申请日：2022-05-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hoseok Lee ,  Sunyoung Kim ,  Younghun Seo

IPC: G11C11/40 ,  G11C11/4091 ,  G11C11/4094 ,  G11C11/4097

CPC classification number: G11C11/4091 ,  G11C11/4094 ,  G11C11/4097

Abstract: A bit line sense amplifier includes a plurality of semiconductor devices including sensing transistors and selection transistors disposed side by side, and configured to sense a voltage change of a bit line and a complementary bit line, and wiring patterns connected to at least one of the plurality of semiconductor devices. The sensing transistors share a source electrode. The selection transistors may be controlled to be complementarily turned on and off. The wiring patterns include a first wiring pattern electrically connecting gate electrodes of the sensing transistors and drain electrodes of the selection transistors, and a second wiring pattern electrically connecting a gate electrode of a sensing transistor and a drain electrode of another sensing transistor.

公开(公告)号：US20240096403A1

公开(公告)日：2024-03-21

申请号：US18325307

申请日：2023-05-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hoseok Lee ,  Younghun Seo ,  Kangsub Jeong ,  Sangyun Kim ,  Dongil Lee

IPC: G11C11/4091 ,  G11C11/408

CPC classification number: G11C11/4091 ,  G11C11/4085 ,  G11C11/4087

Abstract: A memory core circuit includes: (i) a memory cell array having sub cell arrays therein, and (ii) a core control circuit having sub peripheral circuits therein, such that each sub peripheral circuit extends underneath a corresponding sub cell array. Each sub cell array includes memory cells respectively connected to wordlines and bitlines. Each sub peripheral circuit includes sub wordline drivers configured to drive the wordlines, bitline sense amplifiers configured to sense voltages of the bitlines, a row decoding circuit configured to control the sub wordline drivers to select one of the wordlines, a power circuit configured to supply power to each sub peripheral circuit, and a control circuit configured to control operation of each sub peripheral circuit. By using a CoP structure that efficiently provides the core control circuit, the size of the memory core circuit may be reduced and a design margin may be enhanced.

公开(公告)号：US20240029782A1

公开(公告)日：2024-01-25

申请号：US18298999

申请日：2023-04-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dongil Lee ,  Younghun Seo ,  Sun Young Kim ,  Hoseok Lee

IPC: G11C11/4091 ,  G11C11/4094

CPC classification number: G11C11/4091 ,  G11C11/4094

Abstract: A method of operating a bit line sense amplifier may include performing a normal precharge operation by charging a bit line, a complementary bit line, a sensing bit line, and a complementary sensing bit line to a precharge voltage, and then performing a first offset compensation operation by connecting the bit line to the sensing bit line, connecting the complementary bit line to the complementary sensing bit line, applying a first internal voltage greater than the precharge voltage to a P-type sense amplifier, and applying a second internal voltage less than the precharge voltage to an N-type sense amplifier. A second offset compensation operation is performed by applying the precharge voltage to the P-type sense amplifier concurrently with applying the second internal voltage to the N-type sense amplifier. A bit line offset detection operation is performed by separating the bit line from the sensing bit line, separating the complementary bit line from the complementary sensing bit line, connecting the sensing bit line to the complementary sensing bit line, and applying the precharge voltage to the N-type sense amplifier.

公开(公告)号：US20250149080A1

公开(公告)日：2025-05-08

申请号：US18784796

申请日：2024-07-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junhee Cho ,  Incheol Nam ,  Kyuchang Kang ,  Sangyun Kim ,  Sunyoung Kim ,  Jongwook Park ,  Hoseok Lee ,  Kangsub Jeong

IPC: G11C11/4091 ,  G11C11/4094

Abstract: A memory device includes a memory cell array, a sense amplifier, a voltage generation circuit and a control circuit. The memory cell array includes a plurality of bit lines to which a plurality of memory cells are connected, and a shielding bit line arranged between the plurality of bit lines and on lower portions of the plurality of bit lines. The sense amplifier is configured to sense and amplify data stored in a memory cell selected from among the plurality of memory cells. The voltage generation circuit is configured to generate a bit line precharge voltage and an internal power voltage based on a power voltage of the memory device. The control circuit is configured to selectively provide the shielding bit line with the bit line precharge voltage or the internal power voltage.

公开(公告)号：US20240161810A1

公开(公告)日：2024-05-16

申请号：US18381115

申请日：2023-10-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： SEUNG-JUN LEE ,  YOUNGHUN SEO ,  Hoseok Lee

IPC: G11C11/4091 ,  G11C11/408 ,  G11C11/4097

CPC classification number: G11C11/4091 ,  G11C11/4087 ,  G11C11/4097

Abstract: A memory device includes a memory cell array which includes a plurality of word lines and a plurality of bit lines; a plurality of column selection lines which extends over the memory cell array and includes a first part of the memory cell array and a second part connected to the first part; a plurality of bit line sense amplifiers each connected to a bit line and configured to sense data stored in a memory cell; a plurality of local sense amplifiers each configured to output the sensed data from one of the bit line sense amplifiers through a column selection transistor connected to a local column selection line; a control logic circuit which generates a row address signal indicating an activation word line and a column address signal indicating an activation bit line; and a column decoder which activates a column selection line based on the column address signal.