公开(公告)号：US11501824B2

公开(公告)日：2022-11-15

申请号：US17002002

申请日：2020-08-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dongil Lee ,  Younghun Seo

IPC: G11C11/4091 ,  G11C11/4094 ,  G11C11/56

Abstract: A volatile memory device includes: a first sense amplifier connected to a first memory cell through a first bit line, and configured to sense 2-bit data stored in the first memory cell; a second sense amplifier connected to a second memory cell through a second bit line, and configured to sense 2-bit data stored in the second memory cell, the second bit line having a length greater than a length of the first bit line; and a driving voltage supply circuit configured to supply a first driving voltage to the first sense amplifier, and supply a second driving voltage to the second sense amplifier, the second driving voltage having a voltage level different from a voltage level of the first driving voltage.

公开(公告)号：US11024365B1

公开(公告)日：2021-06-01

申请号：US16782365

申请日：2020-02-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Younghun Seo ,  Bokyeon Won ,  Dongil Lee

IPC: G11C7/00 ,  G11C11/4091 ,  G11C11/4076 ,  G11C11/4094

Abstract: Provided are a time interleaved sampling sense amplifier and a memory device including the same. The sense amplifier senses a voltage stored in the memory cell as 1-bit data or a most significant bit (MSB) and a least significant bit (LSB) of 2-bit data and latches the same to a sensing bit line and a complementary sensing bit line. The sense amplifier includes a first sense amplifier that samples a voltage change of a first bit line when the odd equalizing signal is disabled and a second sense amplifier that samples a voltage change of a second bit line when the even equalizing signal is disabled. The first sense amplifier and the second sense amplifier are alternately arranged, and the odd equalizing signal and the even equalizing signal are disabled with a certain time difference.

公开(公告)号：US20240096403A1

公开(公告)日：2024-03-21

申请号：US18325307

申请日：2023-05-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hoseok Lee ,  Younghun Seo ,  Kangsub Jeong ,  Sangyun Kim ,  Dongil Lee

IPC: G11C11/4091 ,  G11C11/408

CPC classification number: G11C11/4091 ,  G11C11/4085 ,  G11C11/4087

Abstract: A memory core circuit includes: (i) a memory cell array having sub cell arrays therein, and (ii) a core control circuit having sub peripheral circuits therein, such that each sub peripheral circuit extends underneath a corresponding sub cell array. Each sub cell array includes memory cells respectively connected to wordlines and bitlines. Each sub peripheral circuit includes sub wordline drivers configured to drive the wordlines, bitline sense amplifiers configured to sense voltages of the bitlines, a row decoding circuit configured to control the sub wordline drivers to select one of the wordlines, a power circuit configured to supply power to each sub peripheral circuit, and a control circuit configured to control operation of each sub peripheral circuit. By using a CoP structure that efficiently provides the core control circuit, the size of the memory core circuit may be reduced and a design margin may be enhanced.

公开(公告)号：US20240029782A1

公开(公告)日：2024-01-25

申请号：US18298999

申请日：2023-04-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dongil Lee ,  Younghun Seo ,  Sun Young Kim ,  Hoseok Lee

IPC: G11C11/4091 ,  G11C11/4094

CPC classification number: G11C11/4091 ,  G11C11/4094

Abstract: A method of operating a bit line sense amplifier may include performing a normal precharge operation by charging a bit line, a complementary bit line, a sensing bit line, and a complementary sensing bit line to a precharge voltage, and then performing a first offset compensation operation by connecting the bit line to the sensing bit line, connecting the complementary bit line to the complementary sensing bit line, applying a first internal voltage greater than the precharge voltage to a P-type sense amplifier, and applying a second internal voltage less than the precharge voltage to an N-type sense amplifier. A second offset compensation operation is performed by applying the precharge voltage to the P-type sense amplifier concurrently with applying the second internal voltage to the N-type sense amplifier. A bit line offset detection operation is performed by separating the bit line from the sensing bit line, separating the complementary bit line from the complementary sensing bit line, connecting the sensing bit line to the complementary sensing bit line, and applying the precharge voltage to the N-type sense amplifier.