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    MEMORY DEVICE FOR CONTROLLING SHIELDING BIT LINES
    1.
    发明申请
    MEMORY DEVICE FOR CONTROLLING SHIELDING BIT LINES 有权

    公开(公告)号：US20250149080A1

    公开(公告)日：2025-05-08

    申请号：US18784796

    申请日：2024-07-25

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Junhee Cho ,  Incheol Nam ,  Kyuchang Kang ,  Sangyun Kim ,  Sunyoung Kim ,  Jongwook Park ,  Hoseok Lee ,  Kangsub Jeong

    IPC: G11C11/4091 ,  G11C11/4094

    Abstract: A memory device includes a memory cell array, a sense amplifier, a voltage generation circuit and a control circuit. The memory cell array includes a plurality of bit lines to which a plurality of memory cells are connected, and a shielding bit line arranged between the plurality of bit lines and on lower portions of the plurality of bit lines. The sense amplifier is configured to sense and amplify data stored in a memory cell selected from among the plurality of memory cells. The voltage generation circuit is configured to generate a bit line precharge voltage and an internal power voltage based on a power voltage of the memory device. The control circuit is configured to selectively provide the shielding bit line with the bit line precharge voltage or the internal power voltage.

    Pumping capacitor and semiconductor memory device including the same
    2.
    发明授权
    Pumping capacitor and semiconductor memory device including the same 有权

    公开(公告)号：US12133372B2

    公开(公告)日：2024-10-29

    申请号：US17683562

    申请日：2022-03-01

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Yooseok Yang ,  Jongwook Park

    IPC: G11C11/34 ,  G11C5/10 ,  G11C5/14 ,  H01L49/02 ,  H10B12/00

    CPC classification number: H10B12/31 ,  G11C5/10 ,  G11C5/14 ,  G11C5/145 ,  H01L28/60

    Abstract: A pumping capacitor is provided. The pumping capacitor includes: first, second, third and fourth electrodes that are separately formed on a substrate; a first pumping capacitor group, wherein i first cell capacitors have lower electrodes formed on the first pad electrode and upper electrodes connected to a plate electrode, and (n−i) first cell capacitors have lower electrodes formed on the second pad electrode and upper electrodes connected to the plate electrode; and a second pumping capacitor group, wherein i second cell capacitors have lower electrodes formed on the fourth pad electrode and upper electrodes connected to the plate electrode, and (n−i) second cell capacitors have lower electrodes formed on the third pad electrode and upper electrodes connected to the plate electrode. The first pumping capacitor group and the second pumping capacitor group are connected in series, and the second pad electrode and the third pad electrode are floated.

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