公开(公告)号：US12133372B2

公开(公告)日：2024-10-29

申请号：US17683562

申请日：2022-03-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yooseok Yang ,  Jongwook Park

IPC: G11C11/34 ,  G11C5/10 ,  G11C5/14 ,  H01L49/02 ,  H10B12/00

CPC classification number: H10B12/31 ,  G11C5/10 ,  G11C5/14 ,  G11C5/145 ,  H01L28/60

Abstract: A pumping capacitor is provided. The pumping capacitor includes: first, second, third and fourth electrodes that are separately formed on a substrate; a first pumping capacitor group, wherein i first cell capacitors have lower electrodes formed on the first pad electrode and upper electrodes connected to a plate electrode, and (n−i) first cell capacitors have lower electrodes formed on the second pad electrode and upper electrodes connected to the plate electrode; and a second pumping capacitor group, wherein i second cell capacitors have lower electrodes formed on the fourth pad electrode and upper electrodes connected to the plate electrode, and (n−i) second cell capacitors have lower electrodes formed on the third pad electrode and upper electrodes connected to the plate electrode. The first pumping capacitor group and the second pumping capacitor group are connected in series, and the second pad electrode and the third pad electrode are floated.

公开(公告)号：US20240170042A1

公开(公告)日：2024-05-23

申请号：US18337507

申请日：2023-06-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yooseok Yang

IPC: G11C11/4074 ,  G11C11/4091 ,  G11C11/4094

CPC classification number: G11C11/4074 ,  G11C11/4091 ,  G11C11/4094

Abstract: A memory device having an architecture of a voltage driver circuit and a decoupling capacitor is disclosed. The memory device includes a peripheral circuit structure and a cell array structure vertically overlapping the peripheral circuit structure thereon. The cell array structure includes a memory cell region including a plurality of transistor structures and a plurality of capacitor structures electrically connected to respective ones of the plurality of transistor structures. The peripheral circuit structure includes a first region including sense amplifiers coupled to a plurality of bitlines of the memory cell region and a second region including a first voltage driver circuit that is configured to generate an internal power supply voltage to provide to sense amplifiers.