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公开(公告)号：US11824534B2
公开(公告)日：2023-11-21
申请号：US17455195
申请日：2021-11-16
Applicant: XILINX, INC.
Inventor： Nakul Narang , Siok Wei Lim , Luhui Chen , Yipeng Wang , Kee Hian Tan
IPC: H04L25/02 , H03K19/17736 , G06F13/10 , H03K19/17788 , H04J3/04
CPC classification number: H03K19/17744 , G06F13/102 , H03K19/17788 , H04J3/047 , H04L25/0272
Abstract: A transmit driver architecture with a test mode (e.g., a JTAG configuration mode), extended equalization range, and/or multiple power supply domains. One example transmit driver circuit generally includes one or more driver unit cells having a differential input node pair configured to receive an input data signal and having a differential output node pair configured to output an output data signal; a plurality of power switches coupled between the differential output node pair and one or more power supply rails; a first set of one or more drivers coupled between a first test node of a differential test data path and a first output node of the differential output node pair; and a second set of one or more drivers coupled between a second test node of the differential test data path and a second output node of the differential output node pair.
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公开(公告)号：US20190123728A1
公开(公告)日：2019-04-25
申请号：US15788617
申请日：2017-10-19
Applicant: Xilinx, Inc.
Inventor： Hai Bing Zhao , Kee Hian Tan , Ping-Chuan Chiang , Yohan Frans
Abstract: A quadrature clock correction (QCC) circuit includes: a first pair of clock correction circuits that output in-phase and anti-in-phase clock signals, respectively, of a four-phase clock signal; a second pair of clock correction circuits that output quadrature-phase and anti-quadrature-phase clock signals, respectively, of the four-phase clock signal; a detector circuit configured to detect duty cycle error and in-phase/quadrature-phase (IQ) phase mismatch in the four-phase clock signal; and a calibration circuit configured to supply a first pair of control signals to each the first pair of clock correction circuits, and a second pair of control signals to each of the second pair of clock correction circuits, to correct both the duty cycle error and the IQ phase mismatch based output of the detector circuit.
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公开(公告)号：US10862714B1
公开(公告)日：2020-12-08
申请号：US16670175
申请日：2019-10-31
Applicant: XILINX, INC.
Inventor： Nakul Narang , Hsung Jai Im , Kee Hian Tan
Abstract: A method for testing on-die capacitors is provided. The method comprises transmitting, during a first time period, a first modulated testing signal from a first transmitter port of a transmitter to a first receiver port of a receiver along a first path of a differential signal, the first receiver port connected to a first on-die capacitor in the receiver along the first path; driving, during the first time period, a constant voltage on a second transmitter port of the transmitter to a second receiver port of the receiver along a second path of the differential signal comprising a second on-die capacitor; and determining whether the first on-die capacitor is functional, based on the first modulated testing signal.
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公开(公告)号：US10598852B1
公开(公告)日：2020-03-24
申请号：US16425009
申请日：2019-05-29
Applicant: Xilinx, Inc.
Inventor： Hai bing Zhao , Kee Hian Tan , Ping-Chuan Chiang , Yipeng Wang , Yohan Frans
Abstract: A data driver includes pre-driver circuitry coupled to a digital-to-analog converter (DAC) via a plurality of bit lines. The pre-driver circuitry is configured to receive a plurality of first voltages corresponding to respective bits of a digital codeword. Each of the first voltages may have one of a first voltage value or a ground potential based on a value of the corresponding bit. The pre-driver circuitry is further configured to drive a plurality of second voltages onto the plurality of bit lines, respectively, by switchably coupling each of the bit lines to ground or a voltage rail based at least in part on the voltage values of the plurality of first voltages. The voltage rail provides a second voltage value that is greater than the first voltage value. The DAC converts the plurality of second voltages to an electrical signal which is an analog representation of the digital codeword.
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公开(公告)号：US09853642B1
公开(公告)日：2017-12-26
申请号：US15234667
申请日：2016-08-11
Applicant: Xilinx, Inc.
Inventor： Kee Hian Tan , Kok Lim Chan , Siok Wei Lim
IPC: H03K3/00 , H03K19/0185 , H03H17/06 , H03M9/00 , H04L25/03
CPC classification number: H03K19/018521 , H03H17/06 , H03M9/00 , H04L25/03343
Abstract: An example output driver includes a plurality of output circuits coupled in parallel between a first voltage supply node and a second voltage supply node. Each of the plurality of output circuits includes a differential input that is coupled to receive a logic signal of a plurality of logic signals and a differential output that is coupled to a common output node. The output driver further includes voltage regulator(s), coupled to the voltage supply node(s), and a current compensation circuit. The current compensation circuit includes a switch coupled in series with a current source, where the switch and the current source are coupled between the first voltage supply node and the second voltage supply node. An event detector is coupled to the switch to supply an enable signal and to control state of the enable signal based on presence of a pattern in the plurality of logic signals.
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Patent Agency Ranking
公开(公告)号：US09742597B1
公开(公告)日：2017-08-22
申请号：US15084351
申请日：2016-03-29
Applicant: Xilinx, Inc.
Inventor： Kun-Yung Chang , Siok Wei Lim , Kee Hian Tan
IPC: H04L25/03
CPC classification number: H04L25/03057 , H04L25/03885 , H04L25/4902 , H04L2025/03363 , H04L2025/03375 , H04L2025/03484 , H04L2025/03764
Abstract: An apparatus includes a decision feedback equalizer configured to receive a parallel signal generated based on a first clock. The decision feedback equalizer includes a first equalization block configured to receive a first symbol of a first set of parallel symbols provided by the parallel signal during a first clock cycle of the first clock. A decision feedback equalization is performed by the first equalization block to the first symbol to provide a first decision to a second equalization block. The second equalization block is configured to receive a second symbol of the first set of parallel symbols and perform a decision feedback equalization to the second symbol using the first decision received from the first equalization block to provide a second decision during the first clock cycle.
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公开(公告)号：US10680592B2
公开(公告)日：2020-06-09
申请号：US15788617
申请日：2017-10-19
Applicant: Xilinx, Inc.
Inventor： Hai Bing Zhao , Kee Hian Tan , Ping-Chuan Chiang , Yohan Frans
Abstract: A quadrature clock correction (QCC) circuit includes: a first pair of clock correction circuits that output in-phase and anti-in-phase clock signals, respectively, of a four-phase clock signal; a second pair of clock correction circuits that output quadrature-phase and anti-quadrature-phase clock signals, respectively, of the four-phase clock signal; a detector circuit configured to detect duty cycle error and in-phase/quadrature-phase (IQ) phase mismatch in the four-phase clock signal; and a calibration circuit configured to supply a first pair of control signals to each the first pair of clock correction circuits, and a second pair of control signals to each of the second pair of clock correction circuits, to correct both the duty cycle error and the IQ phase mismatch based output of the detector circuit.
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公开(公告)号：US20180041232A1
公开(公告)日：2018-02-08
申请号：US15227853
申请日：2016-08-03
Applicant: Xilinx, Inc.
Inventor： Siok Wei Lim , Kok Lim Chan , Kee Hian Tan , Hongyuan Zhao , Chin Yang Koay , Yohan Frans , Kun-Yung Chang
IPC: H04B1/04 , H03M9/00 , H02M3/158 , H03K17/687
CPC classification number: H04B1/04 , H02M3/158 , H03K17/163 , H03K17/6872 , H03K19/0175 , H03M9/00
Abstract: A driver circuit includes a plurality of output circuits coupled in parallel between a differential input and a differential output and having a first common node and a second common node. Each of the plurality of output circuits includes a series combination of a pair of inverters and a pair of resistors, coupled between the differential input and the differential output; first source terminals of the pair of inverters coupled to the first common node; and second source terminals of the pair of inverters coupled to the second common node. The driver circuit further includes a first voltage regulator having an output coupled to the first common node of the plurality of output circuits; a second voltage regulator having an output coupled to the second common node of the plurality of circuits; and a current compensation circuit coupled between the outputs of the first voltage regulator and the second voltage regulator.
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公开(公告)号：US10712770B1
公开(公告)日：2020-07-14
申请号：US16042785
申请日：2018-07-23
Applicant: Xilinx, Inc.
Inventor： Ping-Chuan Chiang , Kee Hian Tan , Arianne B. Roldan , Nakul Narang , Yipeng Wang , Yohan Frans , Kun-Yung Chang
Abstract: Apparatus and associated methods relate to a high-speed data serializer with a clock calibration module including a main multiplexer (MMUX), a replicated multiplexer (RMUX), a duty cycle calibration module (DCC), and a set of adjustable delay lines (ADLs), the ADLs generating calibrated clocks from a set of system clocks, the DCC sensing duty cycle and phase of the calibrated clocks. In an illustrative example, the DCC may generate error signals indicative of deviation from an expected duty cycle using low-pass filters. The error signals control the ADLs, which may provide continuous corrections to the calibrated clocks, for example. The MMUX and RMUX may receive the calibrated clocks, the RMUX generating a duty cycle indicating clock-to-data phasing, the MMUX providing live data multiplexing, for example. Various multiplexer calibration schemes may reduce jitter, which may facilitate increased data rates associated with high-speed serial data streams.
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公开(公告)号：US10651933B1
公开(公告)日：2020-05-12
申请号：US16421425
申请日：2019-05-23
Applicant: Xilinx, Inc.
Inventor： Ping-Chuan Chiang , Kee Hian Tan , Gourav Modi , Nakul Narang , Haibing Zhao , Yohan Frans
IPC: H04B10/079 , G02F1/025 , G02F1/015
Abstract: Systems and methods for calibrating a ring modulator are described. A system may include a controller configured to provide a first test signal to the ring modulator, determine a first candidate temperature control signal for a heater of the ring modulator when the first test signal is provided to the ring modulator, determine a first optical swing of an optical signal at a drop port of the ring modulator, determine a second candidate temperature control signal for the heater when the first test signal is provided to the ring modulator, determine a second optical swing of an optical signal at the drop port, select an optimal optical swing from the first optical swing and the second optical swing, and select one of the first candidate temperature control signal or the second candidate temperature control signal based on the optimal optical swing selected.
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