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    Communication between integrated circuit (IC) dies in wafer-level fan-out package
    1.
    发明授权
    Communication between integrated circuit (IC) dies in wafer-level fan-out package 有权

    公开(公告)号：US11721651B2

    公开(公告)日：2023-08-08

    申请号：US17037363

    申请日：2020-09-29

    Applicant: XILINX, INC.

    Inventor： Chi Fung Poon ,  Asma Laraba ,  Parag Upadhyaya

    IPC: H01L23/66 ,  H01L23/538 ,  H01L25/16

    CPC classification number: H01L23/66 ,  H01L23/5386 ,  H01L25/16 ,  H01L2224/02379

    Abstract: Examples described herein generally relate to communication between integrated circuit (IC) dies in a wafer-level fan-out package. In an example, an electronic device includes a wafer-level fan-out package. The wafer-level fan-out package includes a first integrated circuit (IC) die, a second IC die, and a redistribution structure. The first IC die includes a transmitter circuit. The second IC die includes a receiver circuit. The redistribution structure includes physical channels electrically connected to and between the transmitter circuit and the receiver circuit. The transmitter circuit is configured to transmit multiple single-ended data signals and a differential clock signal through the physical channels to the receiver circuit. The receiver circuit is configured to capture data from the multiple single-ended data signals using a first single-ended clock signal based on the differential clock signal.

    LOW NOISE QUADRATURE SIGNAL GENERATION
    2.
    发明申请
    LOW NOISE QUADRATURE SIGNAL GENERATION 有权

    公开(公告)号：US20210152180A1

    公开(公告)日：2021-05-20

    申请号：US16688130

    申请日：2019-11-19

    Applicant: Xilinx, Inc.

    Inventor： Jaewook Shin ,  Parag Upadhyaya ,  Shaojun MA

    IPC: H03L7/24 ,  H03K3/03 ,  H03L7/099 ,  H03L7/083 ,  H03B5/12 ,  H04L7/033 ,  G06F1/08

    Abstract: A quadrature clock generator is disclosed. The quadrature clock generator may include a first injection-locked oscillator, a phase interpolator, and a second injection-locked oscillator. The first injection-locked oscillator may generate a first plurality clock signals from a first reference clock signal. The phase interpolator may generate a second reference clock signal from the first plurality of clock signals, and the second injection-locked oscillator may generate a second plurality of clock signals from the second reference clock signal. A first quadrature clock signal may be selected from the first plurality of clock signals and a second quadrature clock signal may be selected from the second plurality of reference clock signals.

    Delta-sigma modulator having expanded fractional input range
    4.
    发明授权
    Delta-sigma modulator having expanded fractional input range 有权

    公开(公告)号：US10291239B1

    公开(公告)日：2019-05-14

    申请号：US16000698

    申请日：2018-06-05

    Applicant: Xilinx, Inc.

    Inventor： Zhaoyin D. Wu ,  Winson Lin ,  Parag Upadhyaya ,  Geoffrey Zhang ,  Kun-Yung Chang

    IPC: H03L7/08 ,  H03L7/197

    Abstract: An example apparatus includes an input circuit including a first adder and a first multiplier, the first adder configured to level-shift an input signal by an amount and the first multiplier configured to multiply output of the adder by a factor. The apparatus further includes a multi-stage noise shaping (MASH) circuit having an input coupled to the first multiplier. The apparatus further includes an output circuit including a second multiplier and a second adder, the second multiplier configured to multiply output of the MASH circuit by a reciprocal of the factor and the second adder configured to level-shift output of the second multiplier by an inverse of the amount.

    Phase-locked loop having sub-sampling phase detector
    7.
    发明授权
    Phase-locked loop having sub-sampling phase detector 有权

    公开(公告)号：US09608644B1

    公开(公告)日：2017-03-28

    申请号：US15172442

    申请日：2016-06-03

    Applicant: Xilinx, Inc.

    Inventor： Mayank Raj ,  Parag Upadhyaya ,  Adebabay M. Bekele

    IPC: H03L7/06 ,  H03L7/087

    CPC classification number: H03L7/087 ,  H03L7/081 ,  H03L7/0895 ,  H03L7/091 ,  H03L7/095 ,  H03L7/1075 ,  H03L7/113

    Abstract: An example phase-locked loop (PLL) circuit includes a voltage controlled oscillator (VCO) configured to generate an output clock based on an oscillator control voltage, a sub-sampling phase detector configured to receive a reference clock and the output clock, and a phase frequency detector configured to receive the reference clock and a feedback clock. The PLL circuit includes a charge pump configured to generate a charge pump current, a multiplexer circuit configured to select either output of the sub-sampling phase detector or output of the phase frequency detector to control the charge pump, and a lock detector configured to receive the reference clock, the feedback clock, and the output of the phase frequency detector to control the multiplexer. The PLL circuit includes a loop filter configured to filter the charge pump current and generate the oscillator control voltage, and a frequency divider configured to generate the reference clock from the output clock.

    Adjustable buffer circuit
    8.
    发明授权
    Adjustable buffer circuit 有权
    可调缓冲电路

    公开(公告)号：US09225332B1

    公开(公告)日：2015-12-29

    申请号：US14681898

    申请日：2015-04-08

    Applicant: Xilinx, Inc.

    Inventor： Wenfeng Zhang ,  Parag Upadhyaya

    IPC: H03K19/094 ,  H03K19/0185

    CPC classification number: H03K19/018514 ,  H03K19/09432

    Abstract: A common mode logic buffer device includes a current source configured to provide a source current. An input stage includes a first MOS transistor pair configured to generate, from the source current and based upon an input differential voltage, a differential current between two output paths. An output stage includes a second MOS transistor pair configured to generate an output differential voltage based upon an effective impedance provided for the each of the two output paths. An adjustment circuit is configured to adjust, in response to a control signal, the effective impedance of the second MOS transistor pair.

    Abstract translation: 共模逻辑缓冲器件包括被配置为提供源极电流的电流源。 输入级包括第一MOS晶体管对，其被配置为从源电流和基于输入差分电压产生两个输出路径之间的差分电流。 输出级包括被配置为基于为两个输出路径中的每一个提供的有效阻抗产生输出差分电压的第二MOS晶体管对。 调整电路被配置为响应于控制信号调整第二MOS晶体管对的有效阻抗。

    Plesiochronous clock generation for parallel wireline transceivers
    9.
    发明授权
    Plesiochronous clock generation for parallel wireline transceivers 有权
    并行有线收发器的同步时钟生成

    公开(公告)号：US08836391B2

    公开(公告)日：2014-09-16

    申请号：US13633584

    申请日：2012-10-02

    Applicant: Xilinx, Inc.

    Inventor： Parag Upadhyaya ,  Jafar Savoj ,  Anthony Torza

    IPC: H03L7/06 ,  H03L7/087 ,  H03L7/089

    CPC classification number: H03L7/087 ,  H03L7/0891 ,  H03L7/10 ,  H03L7/1976 ,  H04J3/0685 ,  H04L27/0014 ,  H04L2027/0059 ,  H04L2027/0067

    Abstract: A method for plesiochronous clock generation for parallel wireline transceivers, includes: inputting, into at least one decoder, at least one digital frequency mismatch number; decoding, with the at least one decoder, the at least one digital frequency mismatch number to obtain at least one digital frequency divider number that represents a transmit frequency associated with at least one signal; inputting the at least one digital frequency divider number into at least one fractional-N phase lock loop; and utilizing, by the at least one fractional-N phase lock loop, the at least one digital frequency divider number and an analog reference signal produced by a reference oscillator to produce a resultant signal at the transmit frequency; wherein the at least one decoder and the at least one fractional-N phase lock loop are contained on a single integrated circuit.

    Abstract translation: 一种用于并行有线收发机的同步时钟产生方法，包括：向至少一个解码器输入至少一个数字频率失配数; 使用所述至少一个解码器解码所述至少一个数字频率失配数，以获得表示与至少一个信号相关联的发射频率的至少一个数字分频器数; 将至少一个数字分频器编号输入到至少一个小数N相锁定环中; 以及利用所述至少一个分数N锁相环使用所述至少一个数字分频器编号和由参考振荡器产生的模拟参考信号，以产生在所述发射频率处的结果信号; 其中所述至少一个解码器和所述至少一个分数N相锁相环包含在单个集成电路上。

    PLESIOCHRONOUS CLOCK GENERATION FOR PARALLEL WIRELINE TRANSCEIVERS
    10.
    发明申请
    PLESIOCHRONOUS CLOCK GENERATION FOR PARALLEL WIRELINE TRANSCEIVERS 有权
    平行线路收发器的时钟产生

    公开(公告)号：US20140091843A1

    公开(公告)日：2014-04-03

    申请号：US13633584

    申请日：2012-10-02

    Applicant: XILINX, INC.

    Inventor： Parag Upadhyaya ,  Jafar Savoj ,  Anthony Torza

    IPC: H03L7/093

    CPC classification number: H03L7/087 ,  H03L7/0891 ,  H03L7/10 ,  H03L7/1976 ,  H04J3/0685 ,  H04L27/0014 ,  H04L2027/0059 ,  H04L2027/0067

    Abstract: A method for plesiochronous clock generation for parallel wireline transceivers, includes: inputting, into at least one decoder, at least one digital frequency mismatch number; decoding, with the at least one decoder, the at least one digital frequency mismatch number to obtain at least one digital frequency divider number that represents a transmit frequency associated with at least one signal; inputting the at least one digital frequency divider number into at least one fractional-N phase lock loop; and utilizing, by the at least one fractional-N phase lock loop, the at least one digital frequency divider number and an analog reference signal produced by a reference oscillator to produce a resultant signal at the transmit frequency; wherein the at least one decoder and the at least one fractional-N phase lock loop are contained on a single integrated circuit.

    Abstract translation: 一种用于并行有线收发机的同步时钟产生方法，包括：向至少一个解码器输入至少一个数字频率失配数; 使用所述至少一个解码器解码所述至少一个数字频率失配数，以获得表示与至少一个信号相关联的发射频率的至少一个数字分频器数; 将至少一个数字分频器编号输入到至少一个小数N相锁定环中; 以及利用所述至少一个分数N锁相环使用所述至少一个数字分频器编号和由参考振荡器产生的模拟参考信号，以产生在所述发射频率处的结果信号; 其中所述至少一个解码器和所述至少一个分数N相锁相环包含在单个集成电路上。

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