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    Power converter module
    2.
    发明授权
    Power converter module 有权

    公开(公告)号：US11601065B1

    公开(公告)日：2023-03-07

    申请号：US17461423

    申请日：2021-08-30

    申请人： TEXAS INSTRUMENTS INCORPORATED

    发明人： Woochan Kim ,  Vivek Kishorechand Arora ,  Makoto Shibuya ,  Kengo Aoya

    IPC分类号： H02M3/00 ,  H02M7/00 ,  H02M7/527 ,  H01L29/16 ,  H01L29/20 ,  H02M3/158

    摘要： A power converter module includes power transistors and a substrate having a first surface and a second surface that opposes the first surface. A thermal pad is situated on the second surface of the substrate, and the thermal pad is configured to be thermally coupled to a heat sink. The power converter module also includes a control module mounted on a first surface of the substrate. The control module also includes control IC chips coupled to the power transistors. A first control IC chip controls a first switching level of the power converter module and a second control IC chip controls a second switching level of the power converter module. Shielding planes overlay the substrate. A first shielding plane is situated between the thermal pad and the first control IC chip and a second shielding plane is situated between the thermal pad and a second control IC chip.

    IC package with half-bridge power module
    3.
    发明授权
    IC package with half-bridge power module 有权

    公开(公告)号：US11387179B2

    公开(公告)日：2022-07-12

    申请号：US16827455

    申请日：2020-03-23

    申请人： TEXAS INSTRUMENTS INCORPORATED

    发明人： Makoto Shibuya ,  Kengo Aoya ,  Woochan Kim ,  Vivek Kishorechand Arora

    IPC分类号： H01L23/498 ,  H01L23/64 ,  H01L49/02 ,  H01L23/00 ,  H01L21/8234 ,  H01L21/48

    摘要： An integrated circuit (IC) package includes a substrate having a first region and a second region. The substrate includes a conductive path between the first region and the second region. The IC package also includes a lead frame having a first member and a second member that are spaced apart. The IC package further includes a half-bridge power module. The half-bridge power module includes a capacitor having a first node coupled to the first member of the lead frame and a second node coupled to the second member of the lead frame. The half-bridge power module also includes a high side die having a high side field effect transistor (FET) embedded therein and a low side die having a low side FET embedded therein. A source of the high side FET is coupled to a drain of the low side FET through the conductive path of the substrate.

    SEMICONDUCTOR PACKAGE WITH MULTILAYER MOLD
    4.
    发明申请
    SEMICONDUCTOR PACKAGE WITH MULTILAYER MOLD 审中-公开

    公开(公告)号：US20200058570A1

    公开(公告)日：2020-02-20

    申请号：US16540943

    申请日：2019-08-14

    申请人： TEXAS INSTRUMENTS INCORPORATED

    发明人： Kengo Aoya ,  Masamitsu Matsuura ,  Takeshi Onogami ,  Hideaki Matsunaga

    IPC分类号： H01L23/31 ,  H01L23/16 ,  H01L23/498 ,  H01L23/053 ,  H01L21/56 ,  H01L21/78 ,  H01L23/00

    摘要： A semiconductor package includes a semiconductor die including an active side, a redistribution layer over the active side of the semiconductor die, the redistribution layer including metal traces electrically connecting die pads on the active side of the semiconductor die to electrical contacts on an external surface of the semiconductor package, and a layered mold covering the semiconductor die opposite the redistribution layer. The layered mold includes a first resin layer adjacent to the redistribution layer, a fiber layer adjacent to the first resin layer and opposite the redistribution layer, and a second resin layer adjacent to the fiber layer and opposite the redistribution layer. A coefficient of thermal expansion (CTE) of the first resin layer is substantially different than a CTE of the second resin layer.

    Leaded wafer chip scale packages
    10.
    发明授权
    Leaded wafer chip scale packages 有权

    公开(公告)号：US11848244B2

    公开(公告)日：2023-12-19

    申请号：US17491394

    申请日：2021-09-30

    申请人： TEXAS INSTRUMENTS INCORPORATED

    发明人： Makoto Shibuya ,  Masamitsu Matsuura ,  Kengo Aoya

    IPC分类号： H01L23/31 ,  H01L23/528 ,  H01L23/00

    CPC分类号： H01L23/3114 ,  H01L23/528 ,  H01L24/08 ,  H01L24/96 ,  H01L2224/08245 ,  H01L2224/08501

    摘要： In examples, a wafer chip scale package (WCSP) comprises a semiconductor die including a device side having circuitry formed therein. The WCSP includes a redistribution layer (RDL) including an insulation layer abutting the device side and a metal trace coupled to the device side and abutting the insulation layer. The WCSP includes a conductive member coupled to the metal trace, the conductive member in a first vertical plane that is positioned no farther than a quarter of a horizontal width of the semiconductor die from a vertical axis extending through a center of the semiconductor die. The WCSP includes a lead coupled to the conductive member and extending horizontally past a second vertical plane defined by a perimeter of the semiconductor die.