公开(公告)号：US20170110552A1

公开(公告)日：2017-04-20

申请号：US15178150

申请日：2016-06-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Yi LEE ,  Cheng-Yen TSAI ,  Da-Yuan LEE

IPC: H01L29/49 ,  H01L29/51 ,  H01L27/088 ,  H01L21/67 ,  H01L21/28 ,  H01L21/285

CPC classification number: H01L29/4966 ,  H01L21/28088 ,  H01L21/28097 ,  H01L21/28518 ,  H01L21/28556 ,  H01L21/28568 ,  H01L21/67167 ,  H01L27/0886 ,  H01L29/517 ,  H01L29/518

Abstract: A method and structure for providing a pre-deposition treatment (e.g., of a work-function layer) to accomplish work function tuning. In various embodiments, a gate dielectric layer is formed over a substrate, and a work-function metal layer is deposited over the gate dielectric layer. The work-function metal layer has a first thickness. A pre-treatment process of the work-function metal layer may then performed, where the pre-treatment process removes an oxidized layer from a top surface of the work-function metal layer to form a treated work-function metal layer. The treated work-function metal layer has a second thickness less than the first thickness. In various embodiments, after performing the pre-treatment process, another metal layer is deposited over the treated work-function metal layer.

公开(公告)号：US20200161443A1

公开(公告)日：2020-05-21

申请号：US16751128

申请日：2020-01-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Yi LEE ,  Cheng-Yen TSAI ,  Da-Yuan LEE

IPC: H01L29/49 ,  H01L29/51 ,  H01L21/67 ,  H01L27/088 ,  H01L21/285 ,  H01L21/28

Abstract: A method and structure for providing a pre-deposition treatment (e.g., of a work-function layer) to accomplish work function tuning. In various embodiments, a gate dielectric layer is formed over a substrate, and a work-function metal layer is deposited over the gate dielectric layer. The work-function metal layer has a first thickness. A pre-treatment process of the work-function metal layer may then performed, where the pre-treatment process removes an oxidized layer from a top surface of the work-function metal layer to form a treated work-function metal layer. The treated work-function metal layer has a second thickness less than the first thickness. In various embodiments, after performing the pre-treatment process, another metal layer is deposited over the treated work-function metal layer.

公开(公告)号：US20190273145A1

公开(公告)日：2019-09-05

申请号：US15909815

申请日：2018-03-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Hang CHIU ,  Chung-Chiang WU ,  Ching-Hwanq SU ,  Da-Yuan LEE ,  Ji-Cheng CHEN ,  Kuan-Ting LIU ,  Tai-Wei HWANG ,  Chung-Yi SU

IPC: H01L29/49 ,  H01L27/088 ,  H01L29/51 ,  H01L21/28 ,  H01L21/285 ,  H01L21/3213

Abstract: Certain embodiments of a semiconductor device and a method of forming a semiconductor device comprise forming a high-k gate dielectric layer over a short channel semiconductor fin. A work function metal layer is formed over the high-k gate dielectric layer. A seamless metal fill layer is conformally formed over the work function metal layer.

公开(公告)号：US20170110551A1

公开(公告)日：2017-04-20

申请号：US15169566

申请日：2016-05-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Yi LEE ,  Cheng-Yen TSAI ,  Da-Yuan LEE

IPC: H01L29/49 ,  H01L27/088 ,  H01L29/78 ,  H01L29/51 ,  H01L21/285 ,  H01L21/28 ,  H01L21/67

CPC classification number: H01L29/4966 ,  H01L21/28088 ,  H01L21/28176 ,  H01L21/28556 ,  H01L21/67167 ,  H01L27/0886 ,  H01L29/517 ,  H01L29/518 ,  H01L29/78

Abstract: A method and structure for providing a pre-deposition treatment (e.g., of a work-function layer) to accomplish work function tuning. In various embodiments, a gate dielectric layer is formed over a substrate and a work-function metal layer is deposited over the gate dielectric layer. Thereafter, a fluorine-based treatment of the work-function metal layer is performed, where the fluorine-based treatment removes an oxidized layer from a top surface of the work-function metal layer to form a treated work-function metal layer. In some embodiments, after performing the fluorine-based treatment, another metal layer is deposited over the treated work-function metal layer.

公开(公告)号：US20160336420A1

公开(公告)日：2016-11-17

申请号：US14714221

申请日：2015-05-15

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chun-Yuan CHOU ,  Chung-Chiang WU ,  Da-Yuan LEE ,  Weng CHANG

IPC: H01L29/49 ,  H01L29/06 ,  H01L21/28 ,  H01L29/78 ,  H01L29/66 ,  H01L21/285

CPC classification number: H01L29/495 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/28562 ,  H01L21/76877 ,  H01L21/76879 ,  H01L29/0649 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: A method of manufacturing a Fin FET includes forming a fin structure including an upper layer. Part of the upper layer is exposed from an isolation insulating layer. A dummy gate structure is formed over part of the fin structure. The dummy gate structure includes a dummy gate electrode layer and a dummy gate dielectric layer. An interlayer insulating layer is formed over the dummy gate structure. The dummy gate structure is removed so that a space is formed. A gate dielectric layer is formed in the space. A first metal layer is formed over the gate dielectric in the space. A second metal layer is formed over the first metal layer in the space. The first and second metal layers are partially removed, thereby reducing a height of the first and second metal layers. A third metal layer is formed over the partially removed first and second metal layers.

Abstract translation: 制造Fin FET的方法包括形成包括上层的鳍结构。 上层的一部分从隔离绝缘层暴露出来。 在鳍部结构的一部分上形成虚拟栅极结构。 虚拟栅极结构包括伪栅极电极层和伪栅极电介质层。 在虚拟栅极结构上形成层间绝缘层。 去除虚拟栅极结构从而形成空间。 在该空间中形成栅介质层。 在空间中的栅电介质上形成第一金属层。 第二金属层形成在空间中的第一金属层之上。 第一和第二金属层被部分去除，从而减小第一和第二金属层的高度。 在部分去除的第一和第二金属层上形成第三金属层。

公开(公告)号：US20180261459A1

公开(公告)日：2018-09-13

申请号：US15979938

申请日：2018-05-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Yen TSAI ,  Hsin-Yi LEE ,  Chung-Chiang WU ,  Da-Yuan LEE ,  Weng CHANG ,  Ming-Hsing TSAI

IPC: H01L21/28 ,  H01L21/768 ,  H01L21/02 ,  C23C14/58 ,  C23C16/56 ,  C23C16/455

CPC classification number: H01L21/28105 ,  C23C14/58 ,  C23C14/5846 ,  C23C14/5873 ,  C23C16/02 ,  C23C16/06 ,  C23C16/45525 ,  C23C16/45527 ,  C23C16/56 ,  H01L21/02697 ,  H01L21/28088 ,  H01L21/28097 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/76838 ,  H01L21/76886 ,  H01L29/4966 ,  H01L29/66795

Abstract: A system for providing a pre-deposition treatment (e.g., of a work-function layer) to accomplish work function tuning. In various embodiments, a gate dielectric layer is formed over a substrate, and a work-function metal layer is deposited over the gate dielectric layer. In some embodiments, a first in-situ process including a pre-treatment process of the work-function metal layer is performed. By way of example, the pre-treatment process removes an oxidized layer of the work-function metal layer to form a treated work-function metal layer. In some embodiments, after performing the first in-situ process, a second in-situ process including a deposition process of another metal layer over the treated work-function metal layer is performed.

公开(公告)号：US20180097085A1

公开(公告)日：2018-04-05

申请号：US15811374

申请日：2017-11-13

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yu-Sheng WANG ,  Chi-Cheng HUNG ,  Da-Yuan LEE ,  Hsin-Yi LEE ,  Kuan-Ting LIU

IPC: H01L29/66 ,  H01L29/49

CPC classification number: H01L29/66545 ,  H01L29/4966 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

Abstract: A field effect transistor includes a channel layer made of a semiconductor and a metal gate structure. The metal gate structure includes a gate dielectric layer, a barrier layer formed on the gate dielectric layer, a work function adjustment layer formed on the barrier layer and made of one of Al and TiAl, a blocking layer formed on the work function adjustment layer and made of TiN, and a body metal layer formed on the blocking layer and made of W. A gate length over the channel layer is in a range from 5 nm to 15 nm, and a thickness of the first conductive layer is in a range of 0.2 nm to 3.0 nm. A range between a largest thickness and a smallest thickness of the first conductive layer is more than 0% and less than 10% of an average thickness of the first conductive layer.

公开(公告)号：US20180090431A1

公开(公告)日：2018-03-29

申请号：US15817281

申请日：2017-11-19

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chung-Chiang WU ,  Chia-Ching LEE ,  Hsueh-Wen TSAU ,  Chun-Yuan CHOU ,  Cheng-Yen TSAI ,  Da-Yuan LEE ,  Ming-Hsing TSAI

IPC: H01L23/528 ,  H01L29/49 ,  H01L21/311 ,  H01L21/768 ,  H01L23/532

CPC classification number: H01L23/528 ,  H01L21/31133 ,  H01L21/31138 ,  H01L21/76861 ,  H01L21/76879 ,  H01L23/485 ,  H01L23/53228 ,  H01L23/53257 ,  H01L23/53261 ,  H01L29/4966

Abstract: A semiconductor structure includes a substrate, a dielectric layer, a metal layer, and a tungsten layer. The dielectric layer is on the substrate and has a recess feature therein. The metal layer is in the recess feature. The metal layer has an oxygen content less than about 0.1 atomic percent. The tungsten layer is in the recess feature and in contact with the metal layer.

公开(公告)号：US20170330829A1

公开(公告)日：2017-11-16

申请号：US15154989

申请日：2016-05-14

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chung-Chiang WU ,  Chia-Ching LEE ,  Hsueh-Wen TSAU ,  Chun-Yuan CHOU ,  Cheng-Yen TSAI ,  Da-Yuan LEE ,  Ming-Hsing TSAI

IPC: H01L23/528 ,  H01L23/532 ,  H01L21/311 ,  H01L21/768 ,  H01L29/49

CPC classification number: H01L23/528 ,  H01L21/31133 ,  H01L21/31138 ,  H01L21/76861 ,  H01L21/76879 ,  H01L23/485 ,  H01L23/53228 ,  H01L23/53257 ,  H01L23/53261 ,  H01L29/4966

Abstract: A semiconductor structure and the method of forming the same are provided. The method of forming a semiconductor structure includes forming a recess feature in a basal layer, forming a metal layer on the basal layer, exposing the metal layer to a tungsten halide gas to form an oxygen-deficient metal layer, and forming a bulk tungsten layer on the oxygen-deficient metal layer.

公开(公告)号：US20190067279A1

公开(公告)日：2019-02-28

申请号：US16173857

申请日：2018-10-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsueh Wen TSAU ,  Chia-Ching LEE ,  Chung-Chiang WU ,  Da-Yuan LEE

IPC: H01L27/088 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/51 ,  H01L29/49 ,  H01L21/02 ,  H01L21/321 ,  H01L21/28 ,  H01L29/78

CPC classification number: H01L21/28088 ,  H01L21/02244 ,  H01L21/28079 ,  H01L21/32115 ,  H01L21/823437 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7848

Abstract: A method of forming a semiconductor device includes forming a plurality of fins on a substrate, forming a polysilicon gate structure, and replacing the polysilicon gate structure with a metal gate structure. Replacing the polysilicon gate structure includes depositing a work function metal layer over the plurality of fins, forming a metal oxide layer over the work function metal layer, and depositing a first metal layer over the metal oxide layer. A first portion of the metal oxide layer is formed within an area between adjacent fins from among the plurality of fins. An example benefit includes reduced diffusion of unwanted and/or detrimental elements from the first metal layer into its underlying layers and consequently, the reduction of the negative impact of these unwanted and/or detrimental elements on the semiconductor device performance.