公开(公告)号：US20230035716A1

公开(公告)日：2023-02-02

申请号：US17387794

申请日：2021-07-28

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Yiqi TANG ,  Rajen Manicon MURUGAN ,  Li JIANG

IPC: H01L23/498 ,  H01L23/13 ,  H01P3/02 ,  H05K1/02

Abstract: In examples, a semiconductor package comprises a ceramic substrate and a horizontal metal layer covered by the ceramic substrate. The metal layer is configured to carry signals in the 5 GHz to 38 GHz frequency range. The package also includes a vertical castellation on an outer surface of the ceramic substrate, the castellation coupled to the metal layer and having a height ranging from 0.10 mm to 0.65 mm.

公开(公告)号：US20220384369A1

公开(公告)日：2022-12-01

申请号：US17335010

申请日：2021-05-31

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Yiqi TANG ,  Li JIANG ,  Rajen Manicon MURUGAN

IPC: H01L23/58 ,  H01L23/552 ,  H01L23/00

Abstract: In examples, a semiconductor package comprises a ceramic substrate and first and second metal layers covered by the ceramic substrate. The first metal layer is configured to carry signals at least in a 20 GHz to 28 GHz frequency range. The package comprises a semiconductor die positioned above the first and second metal layers and coupled to the first metal layer. The package comprises a ground shield positioned in a horizontal plane between the semiconductor die and the first metal layer, the ground shield including an orifice above a portion of the first metal layer. The package includes a metal seal ring coupled to a top surface of the ceramic substrate, the metal seal ring having a segment that is vertically aligned with a segment of the ground shield. The segment of the ground shield is between the orifice of the ground shield and a horizontal center of the ground shield. The package comprises a metal lid coupled to a top surface of the metal seal ring.

公开(公告)号：US20240047330A1

公开(公告)日：2024-02-08

申请号：US18484310

申请日：2023-10-10

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Jonathan Almeria NOQUIL ,  Makarand Ramkrishna KULKARNI ,  Osvaldo Jorge LOPEZ ,  Yiqi TANG ,  Rajen Manicon MURUGAN ,  Liang WAN

IPC: H01L23/498

CPC classification number: H01L23/49822 ,  H01L23/49844 ,  H01L2224/13147 ,  H01L2224/16238 ,  H01L24/13

Abstract: In some examples, a semiconductor package comprises a multi-layer package substrate. The multi-layer package substrate includes first and second metal layers, the first metal layer positioned above the second metal layer and coupled to the second metal layer by way of a via. The substrate also includes a dielectric covering at least part of the first and second metal layers and the via. The package includes a plated metal layer plated on at least part of the first metal layer and positioned above the dielectric, a combination of the first metal layer and the plated metal layer being thicker than the second metal layer. The package includes a semiconductor die having a device side, the device side vertically aligned with and coupled to the plated metal layer.

公开(公告)号：US20230101847A1

公开(公告)日：2023-03-30

申请号：US17491378

申请日：2021-09-30

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Chittranjan Mohan GUPTA ,  Yiqi TANG ,  Rajen Manicon MURUGAN ,  Jie CHEN ,  Tianyi LUO

IPC: H01L25/065 ,  H01L23/31 ,  H01L23/00 ,  H01L23/498 ,  H01L25/00 ,  H01L21/56

Abstract: In examples, a semiconductor package comprises a substrate and multiple columns of semiconductor dies positioned approximately in parallel along a length of the substrate. The package also includes multiple passive components positioned between the multiple columns of semiconductor dies, the multiple passive components angled between 30 and 60 degrees relative to the length of the substrate, a pair of the multiple passive components having a gap therebetween that is configured to permit mold compound flow through capillary action. The package also includes a mold compound covering the substrate, the multiple columns of semiconductor dies, and the multiple passive components.

公开(公告)号：US20220181241A1

公开(公告)日：2022-06-09

申请号：US17334491

申请日：2021-05-28

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Jonathan Almeria NOQUIL ,  Makarand Ramkrishna KULKARNI ,  Osvaldo Jorge LOPEZ ,  Yiqi TANG ,  Rajen Manicon MURUGAN ,  Liang WAN

IPC: H01L23/498

Abstract: In some examples, a semiconductor package comprises a multi-layer package substrate. The multi-layer package substrate includes first and second metal layers, the first metal layer positioned above the second metal layer and coupled to the second metal layer by way of a via. The substrate also includes a dielectric covering at least part of the first and second metal layers and the via. The package includes a plated metal layer plated on at least part of the first metal layer and positioned above the dielectric, a combination of the first metal layer and the plated metal layer being thicker than the second metal layer. The package includes a semiconductor die having a device side, the device side vertically aligned with and coupled to the plated metal layer.

公开(公告)号：US20240258212A1

公开(公告)日：2024-08-01

申请号：US18161451

申请日：2023-01-30

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Rajen MURUGAN ,  Yiqi TANG ,  Sylvester ANKAMAH-KUSI

IPC: H01L23/495 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L23/49562 ,  H01L21/565 ,  H01L23/3114 ,  H01L24/16 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/16265 ,  H01L2224/48175 ,  H01L2224/48265 ,  H01L2224/49107 ,  H01L2224/49421 ,  H01L2224/49427 ,  H01L2924/1205 ,  H01L2924/1206

Abstract: A packaged semiconductor device includes a lead frame and a semiconductor die. The semiconductor die has first and second opposing sides, and the first side of the die is mounted to the lead frame. A first set of bond wires and/or bump bonds are configured to electrically couple the die to the lead frame. A passive circuit element is on a substrate, and the substrate is mounted to the second side of the die. A second set of bond wires and/or bump bonds are configured to electrically couple the passive circuit element to the die. A molding material is configured to encapsulate the passive circuit element, the die, and at least a portion of the lead frame.

公开(公告)号：US20240113050A1

公开(公告)日：2024-04-04

申请号：US17956798

申请日：2022-09-29

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Juan HERBSOMMER ,  Yiqi TANG ,  Rajen Manicon MURUGAN

IPC: H01L23/66 ,  H01Q1/22 ,  H01Q13/02

CPC classification number: H01L23/66 ,  H01Q1/2283 ,  H01Q13/02 ,  H01L2223/6627 ,  H01L2223/6677

Abstract: In some examples, a semiconductor package includes a semiconductor die; a conductive member coupled to the semiconductor die; and a multi-layer package substrate. The multi-layer package substrate includes a first horizontal metal layer to provide a ground connection; a second horizontal metal layer above the first horizontal metal layer; vertical members coupling to the first and second horizontal metal layers; and a mold compound covering the first and second horizontal metal layers and the vertical members. The first horizontal metal layer, the second horizontal metal layer, and the vertical members together form a structure including a conductive strip coupled to the conductive member, a transition member coupled to the conductive strip, a waveguide coupled to the transition member, and a horn antenna coupled to the waveguide.

公开(公告)号：US20230402356A1

公开(公告)日：2023-12-14

申请号：US17838797

申请日：2022-06-13

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Yiqi TANG ,  Rajen Manicon MURUGAN

IPC: H01L23/495 ,  H01L23/48 ,  H01L21/48

CPC classification number: H01L23/49589 ,  H01L23/481 ,  H01L21/4821 ,  H01L23/49548 ,  H01L23/49586

Abstract: A routable lead frame (RLF) substrate has a conductive layer having first- and second-side traces having first fingers and second fingers, respectively, which are interdigitated with each other. A via layer is over the conductive layer. A first-side conductive via of the via layer is conductively coupled to the first-side trace. A second-side conductive via of the via layer is conductively coupled to the second-side trace. Dielectric molding material is disposed between the interdigitated fingers of the conductive layer and between the first-side conductive via and the second-side conductive via. The fingers and vias form an interdigital capacitor (IDC) useful in impedance matching and filtering.

公开(公告)号：US20230145761A1

公开(公告)日：2023-05-11

申请号：US18148627

申请日：2022-12-30

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Yiqi TANG ,  Liang WAN ,  William Todd HARRISON ,  Manu Joseph PRAKUZHY ,  Rajen Manicon MURUGAN

IPC: H01L23/495 ,  H02M3/158 ,  H01L23/00

CPC classification number: H01L23/49575 ,  H01L23/49562 ,  H01L23/49524 ,  H02M3/158 ,  H01L24/32 ,  H01L2224/32245

Abstract: In some examples, a direct current (DC)-DC power converter package comprises a controller, a conductive member, and a first field effect transistor (FET) coupled to the controller and having a first source and a first drain, the first FET coupled to a first portion of the conductive member. The package also comprises a second FET coupled to the controller and having a second source and a second drain, the second FET coupled to a second portion of the conductive member, the first and second portions of the conductive member being non-overlapping in a horizontal plane. The first and second FETs are non-overlapping.

公开(公告)号：US20240145363A1

公开(公告)日：2024-05-02

申请号：US17977091

申请日：2022-10-31

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Vivek SRIDHARAN ,  Yiqi TANG ,  Blake TRAVIS ,  Dibyajat MISHRA ,  Deepa KOTE

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L23/49816 ,  H01L23/3171 ,  H01L23/3185 ,  H01L23/49838 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/20 ,  H01L24/24 ,  H01L24/73 ,  H01L23/49833 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16014 ,  H01L2224/16227 ,  H01L2224/17132 ,  H01L2224/17133 ,  H01L2224/17177 ,  H01L2224/215 ,  H01L2224/2401 ,  H01L2224/2405 ,  H01L2224/24226 ,  H01L2224/244 ,  H01L2224/73209 ,  H01L2924/15311 ,  H01L2924/182

Abstract: In examples, a semiconductor package comprises a semiconductor die having a device side comprising circuitry formed therein; a passivation layer abutting the device side; first and second horizontal metal members coupled to the device side by way of vias extending through the passivation layer, the first and second horizontal metal members having thicknesses ranging from 4 microns to 25 microns; first and second metal posts coupled to and vertically aligned with the first and second metal members, respectively, the first and second metal posts having vertical thicknesses ranging from 10 microns to 80 microns; first and second solder bumps coupled to the first and second metal posts, respectively; and a ball grid array (BGA) substrate coupled to the first and second solder bumps. The BGA substrate comprises a substrate member; first and second horizontal top metal members abutting the substrate and coupled to the first and second solder bumps, respectively; first and second vias coupled to the first and second horizontal top metal members and extending through the substrate member; and first and second horizontal bottom metal members abutting the substrate and coupled to the first and second vias, respectively. The first horizontal top metal member, the first via, and the first horizontal bottom metal member are electrically coupled to a signal terminal of the semiconductor die and are configured to provide signal currents. The second horizontal top metal member, the second via, and the second horizontal bottom metal member are electrically coupled to a power terminal of the semiconductor die and are configured to provide power currents.