公开(公告)号：US20250126813A1

公开(公告)日：2025-04-17

申请号：US18680535

申请日：2024-05-31

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Sylvester ANKAMAH-KUSI ,  Jonathan Almeria NOQUIL ,  Rajen Manicon MURUGAN

IPC: H01F27/28 ,  H01F27/32 ,  H01F41/04 ,  H01F41/12

Abstract: In examples, a semiconductor package comprises a semiconductor die, and an inductor coupled to the semiconductor die. The inductor comprises a first metal coil having a first end coupled to the semiconductor die and a second end; a second metal coil vertically spaced from the first metal coil and having a third end coupled to the second end and a fourth end coupled to the semiconductor die; a magnetic mold compound (MMC) between the first and second metal coils, the MMC including conductive ions; and an insulative layer between the first and metal coils.

公开(公告)号：US20240222207A1

公开(公告)日：2024-07-04

申请号：US18091349

申请日：2022-12-29

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Michael LUEDERS ,  Giacomo CALABRESE ,  Jonathan Almeria NOQUIL

IPC: H01L23/13 ,  G02B6/12 ,  H01F27/26 ,  H01F27/28 ,  H01L21/48 ,  H01L23/498 ,  H01L25/16

CPC classification number: H01L23/13 ,  G02B6/12004 ,  H01F27/266 ,  H01F27/2804 ,  H01L21/4857 ,  H01L23/49822 ,  H01L23/49838 ,  H01L25/16 ,  H01L28/10 ,  H01F2027/2809 ,  H01L23/49894

Abstract: In examples, a packaged integrated circuit (IC) comprises a package substrate having opposite first and second surfaces and including metal interconnects surrounded by an insulation material. The package substrate includes a depression region that extends from the first surface, and the depression region includes a material different from the insulation material and the metal interconnects. The packaged IC also comprises a semiconductor die on part of the first surface adjacent to the depression region. The semiconductor die includes circuitry coupled to the metal interconnects. The packaged IC also comprises a mold compound covering the semiconductor die and the depression region.

公开(公告)号：US20240047330A1

公开(公告)日：2024-02-08

申请号：US18484310

申请日：2023-10-10

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Jonathan Almeria NOQUIL ,  Makarand Ramkrishna KULKARNI ,  Osvaldo Jorge LOPEZ ,  Yiqi TANG ,  Rajen Manicon MURUGAN ,  Liang WAN

IPC: H01L23/498

CPC classification number: H01L23/49822 ,  H01L23/49844 ,  H01L2224/13147 ,  H01L2224/16238 ,  H01L24/13

Abstract: In some examples, a semiconductor package comprises a multi-layer package substrate. The multi-layer package substrate includes first and second metal layers, the first metal layer positioned above the second metal layer and coupled to the second metal layer by way of a via. The substrate also includes a dielectric covering at least part of the first and second metal layers and the via. The package includes a plated metal layer plated on at least part of the first metal layer and positioned above the dielectric, a combination of the first metal layer and the plated metal layer being thicker than the second metal layer. The package includes a semiconductor die having a device side, the device side vertically aligned with and coupled to the plated metal layer.

公开(公告)号：US20220181241A1

公开(公告)日：2022-06-09

申请号：US17334491

申请日：2021-05-28

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Jonathan Almeria NOQUIL ,  Makarand Ramkrishna KULKARNI ,  Osvaldo Jorge LOPEZ ,  Yiqi TANG ,  Rajen Manicon MURUGAN ,  Liang WAN

IPC: H01L23/498

Abstract: In some examples, a semiconductor package comprises a multi-layer package substrate. The multi-layer package substrate includes first and second metal layers, the first metal layer positioned above the second metal layer and coupled to the second metal layer by way of a via. The substrate also includes a dielectric covering at least part of the first and second metal layers and the via. The package includes a plated metal layer plated on at least part of the first metal layer and positioned above the dielectric, a combination of the first metal layer and the plated metal layer being thicker than the second metal layer. The package includes a semiconductor die having a device side, the device side vertically aligned with and coupled to the plated metal layer.

公开(公告)号：US20200168533A1

公开(公告)日：2020-05-28

申请号：US16200278

申请日：2018-11-26

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Jonathan Almeria NOQUIL ,  Osvaldo Jorge LOPEZ ,  Tianyi LUO

IPC: H01L23/495 ,  H01L23/40 ,  H01L23/373 ,  H01L25/065

Abstract: A semiconductor package comprises a first die thermally coupled to a first thermally conductive device. The first thermally conductive device has a first surface exposed to an exterior of the semiconductor package. The package comprises a second die thermally coupled to a second thermally conductive device, the second thermally conductive device having a second surface exposed to an exterior of the semiconductor package. The first and second dies are positioned in different horizontal planes.