公开(公告)号：US20200258825A1

公开(公告)日：2020-08-13

申请号：US16787327

申请日：2020-02-11

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Yiqi TANG ,  Liang WAN ,  William Todd HARRISON ,  Manu Joseph PRAKUZHY ,  Rajen Manicon MURUGAN

IPC: H01L23/495 ,  H01L23/00 ,  H02M3/158

Abstract: In some examples, a direct current (DC)-DC power converter package comprises a controller, a conductive member, and a first field effect transistor (FET) coupled to the controller and having a first source and a first drain, the first FET coupled to a first portion of the conductive member. The package also comprises a second FET coupled to the controller and having a second source and a second drain, the second FET coupled to a second portion of the conductive member, the first and second portions of the conductive member being non-overlapping in a horizontal plane. The first and second FETs are non-overlapping.

公开(公告)号：US20230145761A1

公开(公告)日：2023-05-11

申请号：US18148627

申请日：2022-12-30

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Yiqi TANG ,  Liang WAN ,  William Todd HARRISON ,  Manu Joseph PRAKUZHY ,  Rajen Manicon MURUGAN

IPC: H01L23/495 ,  H02M3/158 ,  H01L23/00

CPC classification number: H01L23/49575 ,  H01L23/49562 ,  H01L23/49524 ,  H02M3/158 ,  H01L24/32 ,  H01L2224/32245

Abstract: In some examples, a direct current (DC)-DC power converter package comprises a controller, a conductive member, and a first field effect transistor (FET) coupled to the controller and having a first source and a first drain, the first FET coupled to a first portion of the conductive member. The package also comprises a second FET coupled to the controller and having a second source and a second drain, the second FET coupled to a second portion of the conductive member, the first and second portions of the conductive member being non-overlapping in a horizontal plane. The first and second FETs are non-overlapping.

公开(公告)号：US20240047330A1

公开(公告)日：2024-02-08

申请号：US18484310

申请日：2023-10-10

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Jonathan Almeria NOQUIL ,  Makarand Ramkrishna KULKARNI ,  Osvaldo Jorge LOPEZ ,  Yiqi TANG ,  Rajen Manicon MURUGAN ,  Liang WAN

IPC: H01L23/498

CPC classification number: H01L23/49822 ,  H01L23/49844 ,  H01L2224/13147 ,  H01L2224/16238 ,  H01L24/13

Abstract: In some examples, a semiconductor package comprises a multi-layer package substrate. The multi-layer package substrate includes first and second metal layers, the first metal layer positioned above the second metal layer and coupled to the second metal layer by way of a via. The substrate also includes a dielectric covering at least part of the first and second metal layers and the via. The package includes a plated metal layer plated on at least part of the first metal layer and positioned above the dielectric, a combination of the first metal layer and the plated metal layer being thicker than the second metal layer. The package includes a semiconductor die having a device side, the device side vertically aligned with and coupled to the plated metal layer.

公开(公告)号：US20220181241A1

公开(公告)日：2022-06-09

申请号：US17334491

申请日：2021-05-28

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Jonathan Almeria NOQUIL ,  Makarand Ramkrishna KULKARNI ,  Osvaldo Jorge LOPEZ ,  Yiqi TANG ,  Rajen Manicon MURUGAN ,  Liang WAN

IPC: H01L23/498

Abstract: In some examples, a semiconductor package comprises a multi-layer package substrate. The multi-layer package substrate includes first and second metal layers, the first metal layer positioned above the second metal layer and coupled to the second metal layer by way of a via. The substrate also includes a dielectric covering at least part of the first and second metal layers and the via. The package includes a plated metal layer plated on at least part of the first metal layer and positioned above the dielectric, a combination of the first metal layer and the plated metal layer being thicker than the second metal layer. The package includes a semiconductor die having a device side, the device side vertically aligned with and coupled to the plated metal layer.