公开(公告)号：US20240145363A1

公开(公告)日：2024-05-02

申请号：US17977091

申请日：2022-10-31

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Vivek SRIDHARAN ,  Yiqi TANG ,  Blake TRAVIS ,  Dibyajat MISHRA ,  Deepa KOTE

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L23/49816 ,  H01L23/3171 ,  H01L23/3185 ,  H01L23/49838 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/20 ,  H01L24/24 ,  H01L24/73 ,  H01L23/49833 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16014 ,  H01L2224/16227 ,  H01L2224/17132 ,  H01L2224/17133 ,  H01L2224/17177 ,  H01L2224/215 ,  H01L2224/2401 ,  H01L2224/2405 ,  H01L2224/24226 ,  H01L2224/244 ,  H01L2224/73209 ,  H01L2924/15311 ,  H01L2924/182

Abstract: In examples, a semiconductor package comprises a semiconductor die having a device side comprising circuitry formed therein; a passivation layer abutting the device side; first and second horizontal metal members coupled to the device side by way of vias extending through the passivation layer, the first and second horizontal metal members having thicknesses ranging from 4 microns to 25 microns; first and second metal posts coupled to and vertically aligned with the first and second metal members, respectively, the first and second metal posts having vertical thicknesses ranging from 10 microns to 80 microns; first and second solder bumps coupled to the first and second metal posts, respectively; and a ball grid array (BGA) substrate coupled to the first and second solder bumps. The BGA substrate comprises a substrate member; first and second horizontal top metal members abutting the substrate and coupled to the first and second solder bumps, respectively; first and second vias coupled to the first and second horizontal top metal members and extending through the substrate member; and first and second horizontal bottom metal members abutting the substrate and coupled to the first and second vias, respectively. The first horizontal top metal member, the first via, and the first horizontal bottom metal member are electrically coupled to a signal terminal of the semiconductor die and are configured to provide signal currents. The second horizontal top metal member, the second via, and the second horizontal bottom metal member are electrically coupled to a power terminal of the semiconductor die and are configured to provide power currents.