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公开(公告)号：US20240407159A1
公开(公告)日：2024-12-05
申请号：US18326228
申请日：2023-05-31
Inventor： Yu-Der Chih , Ya-Chin King , Chrong Lin , Jonathan Tsung-Yung Chang , Yun-Sheng Chen , May-Be Chen , Hsin-Yuan Yu
IPC: H10B20/25
Abstract: A memory device is disclosed. The memory device includes a memory cell comprising: a transistor; and a plurality of pairs of resistors coupled to the transistor in series, each of the pairs of resistors including a first resistor and a second resistor. The transistor is formed along a major surface of a substrate. At least a first one of the pairs of resistors are formed in a first one of a plurality of metallization layers disposed above the transistor. At least a second one of the pairs of resistors are formed in a second one of the plurality of metallization layers, the second metallization layer being disposed above the first metallization layer.
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Patent Agency Ranking
公开(公告)号：US20230253040A1
公开(公告)日：2023-08-10
申请号：US18301745
申请日：2023-04-17
Inventor： Yu-Der Chih , Jonathan Tsung-Yung Chang , Yun-Sheng Chen , May-Be Chen , Ya-Chin King , Wen Zhang Lin , Chrong Lin , Hsin-Yuan Yu
CPC classification number: G11C13/004 , G11C13/0069 , H10B63/30 , H10N70/253 , G11C2013/0045 , G11C2013/0078
Abstract: Disclosed herein are related to a memory cell including one or more programmable resistors and a control transistor. In one aspect, a programmable resistor includes a gate structure and one or more source/drain structures for forming a transistor. A resistance of the programmable resistor may be set by applying a voltage to the gate structure, while the control transistor is enabled. Data stored by the programmable resistor can be read by sensing current through the programmable resistor, while the control transistor is disabled. In one aspect, the one or more programmable resistors and the control transistor are implemented by same type of components, allowing the memory cell to be formed in a compact manner through a simplified the fabrication process.
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公开(公告)号：US20220252989A1
公开(公告)日：2022-08-11
申请号：US17560039
申请日：2021-12-22
Inventor： Yu-Der Chih , May-Be Chen , Ya-Chin King , Chrong Jung Lin , Burn Jeng Lin , Bo Yu Lin
IPC: G03F7/20 , H01L21/66 , H01L21/027
Abstract: A semiconductor fabrication apparatus and a method of using the same are disclosed. In one aspect, the apparatus includes a holder configured to place a substrate and a radiation source configured to provide radiation to transfer a pattern onto the substrate. The apparatus also includes a plurality of sensing devices configured to provide a reference signal based on an intensity of the radiation when the substrate is not present. The apparatus further includes a controller, operatively coupled to the plurality of sensing devices, configured to adjust the intensity of the radiation based on the reference signal.
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公开(公告)号：US12009029B2
公开(公告)日：2024-06-11
申请号：US18185312
申请日：2023-03-16
Inventor： Yu-Der Chih , Meng-Fan Chang , May-Be Chen , Cheng-Xin Xue , Je-Syu Liu
CPC classification number: G11C13/004 , G06F7/5443 , G11C7/06 , G11C7/1051 , G11C7/1063 , G11C7/14 , G11C13/0069 , G11C2013/0054
Abstract: A system is provided. The system includes a multiply-and-accumulate circuit and a local generator. The multiply-and-accumulate circuit is coupled to a memory array and generates a multiply-and-accumulate signal indicating a computational output of the memory array. The local generator is coupled to the memory array and generates at least one reference signal at a node in response to one of a plurality of global signals that are generated according to a number of the computational output. The local generator is further configured to generate an output signal according to the signal and a summation of the at least one reference signal at the node.
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公开(公告)号：US11943936B2
公开(公告)日：2024-03-26
申请号：US17400615
申请日：2021-08-12
Inventor： Yu-Der Chih , May-Be Chen , Yun-Sheng Chen , Jonathan Tsung-Yung Chang , Wen Zhang Lin , Chrong Jung Lin , Ya-Chin King , Chieh Lee , Wang-Yi Lee
CPC classification number: H10B63/30 , H01L29/401 , H01L29/785
Abstract: A semiconductor device and a method of manufacturing the same are provided. The semiconductor device includes a first transistor, a first resistive random access memory (RRAM) resistor, and a second RRAM resistor. The first resistor includes a first resistive material layer, a first electrode shared by the second resistor, and a second electrode. The second resistor includes the first electrode, a second resistive material layer, and a third electrode. The first electrode is electrically coupled to the first transistor.
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公开(公告)号：US11621040B2
公开(公告)日：2023-04-04
申请号：US17365732
申请日：2021-07-01
Inventor： Yu-Der Chih , Meng-Fan Chang , May-Be Chen , Cheng-Xin Xue , Je-Syu Liu
Abstract: A system includes a global generator and local generators. The global generator is coupled to a memory array, and is configured to generate global signals, according to a number of a computational output of the memory array. The local generators are coupled to the global generator and the memory array, and are configured to generate local signals, according to the global signals. Each one of the local generators includes a first reference circuit and a local current mirror. The first reference circuit is coupled to the global generator, and is configured to generate a first reference signal at a node, in response to a first global signal of the global signals. The local current mirror is coupled to the first reference circuit at the node, and is configured to generate the local signals, by mirroring a summation of at least one signal at the node.
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