公开(公告)号：US09984886B2

公开(公告)日：2018-05-29

申请号：US15001568

申请日：2016-01-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yoon-Hae Kim ,  Hwa-Sung Rhee ,  Keun-Hwi Cho

IPC: H01L27/088 ,  H01L21/285 ,  H01L21/768

CPC classification number: H01L21/28518 ,  H01L21/76843 ,  H01L21/76855 ,  H01L21/76897 ,  H01L27/0886

Abstract: A semiconductor device includes a gate structure extending in a second direction on a substrate, a source/drain layer disposed on a portion of the substrate adjacent the gate structure in a first direction crossing the second direction, a first conductive contact plug on the gate structure, and a second contact plug structure disposed on the source/drain layer. The second contact plug structure includes a second conductive contact plug and an insulation pattern, and the second conductive contact plug and the insulation pattern are disposed in the second direction and contact each other. The first conductive contact plug and the insulation pattern are adjacent to each other in the first direction. The first and second conductive contact plugs are spaced apart from each other.

公开(公告)号：US08981489B2

公开(公告)日：2015-03-17

申请号：US14102736

申请日：2013-12-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junjie Xiong ,  Yoon-Hae Kim ,  Hong-Seong Kang ,  Yoon-Seok Lee ,  You-Shin Choi

IPC: H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119 ,  H01L27/06 ,  H01L49/02

CPC classification number: H01L27/0629 ,  H01L28/20 ,  H01L28/24

Abstract: Semiconductor devices including a resistor structure is provided. The semiconductor device may include a gate structure on an active region, a resistor structure on a field region and a first interlayer insulating layer on the gate structure and the resistor structure. The semiconductor devices may also include a resistor trench plug vertically penetrating through the first interlayer insulating layer and contacting the resistor structure and a second interlayer insulating layer on the first interlayer insulating layer and the resistor trench plug. Further, the semiconductor devices may include a resistor contact plug vertically penetrating through the first and second interlayer insulating layers and contacting the resistor structure.

Abstract translation: 提供了包括电阻器结构的半导体器件。 半导体器件可以包括有源区上的栅极结构，场区上的电阻结构以及栅结构上的第一层间绝缘层和电阻结构。 半导体器件还可以包括垂直穿透第一层间绝缘层并且与第一层间绝缘层和电阻器沟槽插塞上的电阻器结构和第二层间绝缘层接触的电阻器沟槽插塞。 此外，半导体器件可以包括垂直穿过第一和第二层间绝缘层并接触电阻器结构的电阻器接触插塞。

公开(公告)号：US08952452B2

公开(公告)日：2015-02-10

申请号：US13692012

申请日：2012-12-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hong-Seong Kang ,  Yoon-Hae Kim ,  Jong-Shik Yoon

IPC: H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119 ,  H01L29/78 ,  H01L29/40 ,  H01L21/768 ,  H01L29/49 ,  H01L29/66 ,  H01L21/8234 ,  H01L29/417 ,  H01L27/088

CPC classification number: H01L29/78 ,  H01L21/7682 ,  H01L21/76897 ,  H01L21/823456 ,  H01L21/823468 ,  H01L27/088 ,  H01L29/401 ,  H01L29/41783 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/4991 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656

Abstract: Semiconductor devices, and a method of manufacturing the same, include a gate insulating film pattern over a semiconductor substrate. A gate electrode is formed over the gate insulating film pattern. A spacer structure is formed on at least one side of the gate electrode and the gate insulating film pattern. The spacer structure includes a first insulating film spacer contacting the gate insulating film pattern, and a second insulating film spacer on an outer side of the first insulating film spacer. The semiconductor device has an air gap between the first insulating film spacer and the second insulating film spacer.

Abstract translation: 半导体器件及其制造方法包括在半导体衬底上的栅极绝缘膜图案。 在栅极绝缘膜图案上形成栅电极。 在栅电极和栅绝缘膜图案的至少一侧上形成间隔结构。 间隔结构包括与栅极绝缘膜图案接触的第一绝缘膜间隔件和在第一绝缘膜间隔件的外侧上的第二绝缘膜间隔件。 半导体器件在第一绝缘膜间隔件和第二绝缘膜间隔件之间具有气隙。

公开(公告)号：US20140167181A1

公开(公告)日：2014-06-19

申请号：US14102736

申请日：2013-12-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junjie Xiong ,  Yoon-Hae Kim ,  Hong-Seong Kang ,  Yoon-Seok Lee ,  You-Shin Choi

IPC: H01L27/06

CPC classification number: H01L27/0629 ,  H01L28/20 ,  H01L28/24

Abstract: Semiconductor devices including a resistor structure is provided. The semiconductor device may include a gate structure on an active region, a resistor structure on a field region and a first interlayer insulating layer on the gate structure and the resistor structure. The semiconductor devices may also include a resistor trench plug vertically penetrating through the first interlayer insulating layer and contacting the resistor structure and a second interlayer insulating layer on the first interlayer insulating layer and the resistor trench plug. Further, the semiconductor devices may include a resistor contact plug vertically penetrating through the first and second interlayer insulating layers and contacting the resistor structure.

Abstract translation: 提供了包括电阻器结构的半导体器件。 半导体器件可以包括有源区上的栅极结构，场区上的电阻结构以及栅结构上的第一层间绝缘层和电阻结构。 半导体器件还可以包括垂直穿透第一层间绝缘层并且与第一层间绝缘层和电阻器沟槽插塞上的电阻器结构和第二层间绝缘层接触的电阻器沟槽插塞。 此外，半导体器件可以包括垂直穿过第一和第二层间绝缘层并接触电阻器结构的电阻器接触插塞。

公开(公告)号：US20130301187A1

公开(公告)日：2013-11-14

申请号：US13941308

申请日：2013-07-12

Applicant: Samsung Electronics Co., Ltd. ,  Infineon Technologies AG

Inventor： Sun-Oo Kim ,  Yoon-Hae Kim

IPC: H01G4/005

CPC classification number: H01G4/005 ,  H01L23/5223 ,  H01L27/0203 ,  H01L28/87 ,  H01L2924/0002 ,  Y10T29/43 ,  H01L2924/00

Abstract: Semiconductor devices and methods of manufacture thereof are disclosed. In a preferred embodiment, a capacitor plate includes a first propeller-shaped portion and a second propeller-shaped portion. A via portion is disposed between the first propeller-shaped portion and the second propeller-shaped portion.

公开(公告)号：US09209177B2

公开(公告)日：2015-12-08

申请号：US13783513

申请日：2013-03-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yoon-Hae Kim ,  Jong-Shik Yoon ,  Young-Gun Ko

IPC: H01L27/12 ,  H01L27/088 ,  H01L21/8234

CPC classification number: H01L27/0886 ,  H01L21/823431

Abstract: Semiconductor devices are provided. The semiconductor devices may include an active pattern and a insulation layer. The semiconductor devices may include a gate that is on the active pattern and that includes a first material, and a dummy gate that is on the insulation layer and that includes a second material different from the first material.

Abstract translation: 提供半导体器件。 半导体器件可以包括有源图案和绝缘层。 半导体器件可以包括位于有源图案上的并且包括第一材料的栅极和位于绝缘层上并且包括不同于第一材料的第二材料的伪栅极。

公开(公告)号：US10410871B2

公开(公告)日：2019-09-10

申请号：US15969137

申请日：2018-05-02

Applicant: SAMSUNG ELECTRONICS CO. , LTD.

Inventor： Yoon-Hae Kim ,  Hwa-Sung Rhee ,  Keun-Hwi Cho

IPC: H01L21/285 ,  H01L21/768 ,  H01L27/088

Abstract: A semiconductor device includes a gate structure extending in a second direction on a substrate, a source/drain layer disposed on a portion of the substrate adjacent the gate structure in a first direction crossing the second direction, a first conductive contact plug on the gate structure, and a second contact plug structure disposed on the source/drain layer. The second contact plug structure includes a second conductive contact plug and an insulation pattern, and the second conductive contact plug and the insulation pattern are disposed in the second direction and contact each other. The first conductive contact plug and the insulation pattern are adjacent to each other in the first direction. The first and second conductive contact plugs are spaced apart from each other.

公开(公告)号：US08969971B2

公开(公告)日：2015-03-03

申请号：US14045034

申请日：2013-10-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junjie Xiong ,  Yoon-Hae Kim ,  Hong-Seong Kang ,  Yoon-Seok Lee ,  You-Shin Choi

IPC: H01L27/06

CPC classification number: H01L27/0629 ,  Y10S257/90

Abstract: Semiconductor devices are provided. A semiconductor device may include a transistor area and a resistor area. The transistor area may include a gate structure. The resistor area may include an insulating layer and a resistor structure on the insulating layer. A top surface of the gate structure and a top surface of the resistor structure may be substantially coplanar.

Abstract translation: 提供半导体器件。 半导体器件可以包括晶体管区域和电阻器区域。 晶体管区域可以包括栅极结构。 电阻器区域可以在绝缘层上包括绝缘层和电阻器结构。 栅极结构的顶表面和电阻器结构的顶表面可以是基本上共面的。

公开(公告)号：US20140017863A1

公开(公告)日：2014-01-16

申请号：US13918475

申请日：2013-06-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yoon-Seok Lee ,  Yoon-Hae Kim ,  Hong-Seong Kang ,  Sung-Ho Son ,  JunJie Xiong ,  You-Shin Choi

IPC: H01L29/66

CPC classification number: H01L29/66477 ,  H01L21/28518 ,  H01L21/76814 ,  H01L23/485 ,  H01L23/5226 ,  H01L23/5228 ,  H01L27/0629 ,  H01L27/1052 ,  H01L28/20 ,  H01L29/41783 ,  H01L29/517 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/66636 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods of manufacturing a semiconductor device including metal gates are provided. The method may include forming a resistor pattern and a dummy gate electrode, which include polysilicon, and forming an impurity region adjacent to the dummy gate electrode. The method may further include replacing the dummy gate electrode with a gate electrode and then forming metal silicide patterns on the resistor pattern and the impurity region.

Abstract translation: 提供了制造包括金属栅极的半导体器件的方法。 该方法可以包括形成包括多晶硅的电阻器图案和虚拟栅极电极，并且形成与虚拟栅电极相邻的杂质区域。 该方法可以进一步包括用栅电极代替伪栅极电极，然后在电阻器图案和杂质区域上形成金属硅化物图案。

公开(公告)号：US09412693B2

公开(公告)日：2016-08-09

申请号：US14174705

申请日：2014-02-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yoon-Hae Kim ,  Jong-Shik Yoon ,  Hwa-Sung Rhee

IPC: H01L27/11 ,  H01L23/525 ,  H01L49/02 ,  H01L23/485 ,  H01L23/522 ,  H01L27/06 ,  H01L21/8234 ,  H01L21/768 ,  H01L23/532

CPC classification number: H01L23/5256 ,  H01L21/76808 ,  H01L21/76895 ,  H01L21/823475 ,  H01L23/485 ,  H01L23/5221 ,  H01L23/5223 ,  H01L23/5228 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/53295 ,  H01L27/0629 ,  H01L28/20 ,  H01L28/60 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes a substrate having a transistor area, a gate structure disposed on the transistor area of the substrate, a first interlayer insulating layer covering the gate structure, a blocking pattern disposed on the first interlayer insulating layer, and a jumper pattern disposed on the blocking pattern. The jumper pattern includes jumper contact plugs vertically penetrating the first interlayer insulating layer to be in contact with the substrate exposed at both sides of the gate structure, and a jumper section configured to electrically connect the jumper contact plugs.

Abstract translation: 半导体器件包括具有晶体管区域的衬底，设置在衬底的晶体管区域上的栅极结构，覆盖栅极结构的第一层间绝缘层，设置在第一层间绝缘层上的阻挡图案，以及布置在 阻塞模式。 跳线图案包括垂直穿过第一层间绝缘层以与暴露在栅极结构两侧的基板接触的跨接触插塞，以及被配置为电连接跨接触头塞的跳线部分。