公开(公告)号：US20230387118A1

公开(公告)日：2023-11-30

申请号：US18094452

申请日：2023-01-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Su Young BAE ,  Jae Yeol SONG ,  Oh Seong KWON ,  Sang Yong KIM

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/49 ,  H01L29/775 ,  H01L21/8238 ,  H01L29/66

CPC classification number: H01L27/092 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/4908 ,  H01L29/775 ,  H01L21/823807 ,  H01L21/823857 ,  H01L29/66545 ,  H01L29/66439

Abstract: A semiconductor device includes a substrate, an active pattern disposed on the substrate and extending in a first horizontal direction, a gate spacer disposed along each of sidewalls of a gate trench on the active pattern and extending in a second horizontal direction different from the first horizontal direction, a first gate insulating layer disposed along a sidewall and a bottom surface of the gate trench, a first conductive layer disposed on the first gate insulating layer inside the gate trench, a second gate insulating layer disposed on the first conductive layer inside the gate trench, and including a material different from a material of the first gate insulating layer, a second conductive layer disposed on the second gate insulating layer inside the gate trench, and a third conductive layer disposed on the second conductive layer so as to fill a remaining inner space of the gate trench.

公开(公告)号：US20180350983A1

公开(公告)日：2018-12-06

申请号：US16100804

申请日：2018-08-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Won Keun CHUNG ,  Jong Ho PARK ,  Seung Ha OH ,  Sang Yong KIM ,  Hoon Joo NA ,  Sang Jin HYUN

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/423 ,  H01L29/51 ,  H01L21/324 ,  H01L29/06 ,  H01L21/283

CPC classification number: H01L29/7831 ,  B82Y10/00 ,  H01L21/283 ,  H01L21/324 ,  H01L29/0653 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/42356 ,  H01L29/42364 ,  H01L29/42392 ,  H01L29/4908 ,  H01L29/511 ,  H01L29/513 ,  H01L29/66439 ,  H01L29/66484 ,  H01L29/66666 ,  H01L29/775 ,  H01L29/7827 ,  H01L29/78696

Abstract: A semiconductor device and a method for fabricating the same are provided. The semiconductor device includes first and second gate stack structures formed in first and second regions, respectively, wherein the first gate stack structure is formed adjacent a first channel region and comprises a first gate insulating film having a first thickness formed on the first channel region, a first function film having a second thickness formed on the first gate insulating film and a first filling film having a third thickness formed on the first function film, wherein the second gate stack structure is formed adjacent a second channel region and comprises a second gate insulating film having the first thickness formed on the second channel region, a second function film having the second thickness formed on the second gate insulating film and a second filling film having the third thickness formed on the second function film, wherein the first and second function films, respectively, comprise TiN and Si concentrations that are different from each other.

公开(公告)号：US20240096954A1

公开(公告)日：2024-03-21

申请号：US18231594

申请日：2023-08-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Il Gyou SHIN ,  Hyun Ho NOH ,  Sang Yong KIM ,  You Bin KIM

IPC: H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L29/0673 ,  H01L29/41733 ,  H01L29/41775 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/775 ,  H01L29/78696

Abstract: A semiconductor device includes an active pattern including: a lower pattern extending in a first direction, and a plurality of sheet patterns spaced apart from the lower pattern in a second direction; a gate structure on the lower pattern and including a gate electrode and a gate insulating film including an interfacial insulating film including a first vertical portion and a horizontal portion. A dimension in a third direction of the first vertical portion is greater than a dimension in the second direction of the horizontal portion. The first vertical portion includes: a first area contacting a source/drain pattern; and a second area provided between the first area and the gate electrode. The interfacial insulating film includes a first element other than silicon, wherein a concentration of the first element in the first area is greater than a concentration of the first element in the second area.

公开(公告)号：US20210013207A1

公开(公告)日：2021-01-14

申请号：US17038964

申请日：2020-09-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae Jung KIM ,  Young Suk CHAI ,  Sang Yong KIM ,  Hoon Joo NA ,  Sang Jin HYUN

IPC: H01L27/092 ,  H01L29/423 ,  B82Y10/00 ,  H01L29/40 ,  H01L29/775 ,  H01L29/06 ,  H01L29/10 ,  H01L29/66 ,  H01L29/08 ,  H01L21/02 ,  H01L21/8238 ,  H01L29/49 ,  H01L29/78

Abstract: A semiconductor device may include a substrate, a first nanowire, a second nanowire, a first gate insulating layer, a second gate insulating layer, a first metal layer and a second metal layer. The first gate insulating layer may be along a periphery of the first nanowire. The second gate insulating layer may be along a periphery of the second nanowire. The first metal layer may be on a top surface of the first gate insulating layer along the periphery of the first nanowire. The first metal layer may have a first crystal grain size. The second metal layer may be on a top surface of the second gate insulating layer along the periphery of the second nanowire. The second metal layer may have a second crystal grain size different from the first crystal grain size.

公开(公告)号：US20180069006A1

公开(公告)日：2018-03-08

申请号：US15452203

申请日：2017-03-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae Jung Kim ,  Young Suk CHAI ,  Sang Yong KIM ,  Hoon Joo NA ,  Sang Jin HYUN

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/10 ,  H01L29/49 ,  H01L21/8238 ,  H01L21/02

CPC classification number: H01L27/0924 ,  B82Y10/00 ,  H01L21/02603 ,  H01L21/823821 ,  H01L21/823842 ,  H01L29/0653 ,  H01L29/0673 ,  H01L29/1054 ,  H01L29/1079 ,  H01L29/401 ,  H01L29/42364 ,  H01L29/42392 ,  H01L29/495 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/7845

Abstract: A semiconductor device may include a substrate, a first nanowire, a second nanowire, a first gate insulating layer, a second gate insulating layer, a first metal layer and a second metal layer. The first gate insulating layer may be along a periphery of the first nanowire. The second gate insulating layer may be along a periphery of the second nanowire. The first metal layer may be on a top surface of the first gate insulating layer along the periphery of the first nanowire. The first metal layer may have a first crystal grain size. The second metal layer may be on a top surface of the second gate insulating layer along the periphery of the second nanowire. The second metal layer may have a second crystal grain size different from the first crystal grain size.

公开(公告)号：US20220254884A1

公开(公告)日：2022-08-11

申请号：US17503764

申请日：2021-10-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jae-Jung KIM ,  Sang Yong KIM ,  Byoung Hoon LEE ,  Chan Hyeong LEE

IPC: H01L29/06 ,  H01L29/423

Abstract: A semiconductor device includes an active pattern disposed on a substrate. A gate insulating film is disposed on the active pattern and extends along the active pattern. A work function adjustment pattern is disposed on the gate insulating film and extends along the gate insulating film. A gate electrode is disposed on the work function adjustment pattern. The work function adjustment pattern includes a first work function adjustment film, a second work function adjustment film that includes aluminum and wraps the first work function adjustment film, and a barrier film including titanium silicon nitride (TiSiN). A silicon concentration of the barrier film is in a range of about 30 at % or less.

公开(公告)号：US20190109135A1

公开(公告)日：2019-04-11

申请号：US16203946

申请日：2018-11-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae Jung KIM ,  Young Suk CHAI ,  Sang Yong KIM ,  Hoon Joo NA ,  Sang Jin HYUN

IPC: H01L27/092 ,  B82Y10/00 ,  H01L29/78 ,  H01L29/66 ,  H01L29/49 ,  H01L29/423 ,  H01L29/40 ,  H01L29/10 ,  H01L29/06 ,  H01L21/8238 ,  H01L21/02 ,  H01L29/775

Abstract: A semiconductor device may include a substrate, a first nanowire, a second nanowire, a first gate insulating layer, a second gate insulating layer, a first metal layer and a second metal layer. The first gate insulating layer may be along a periphery of the first nanowire. The second gate insulating layer may be along a periphery of the second nanowire. The first metal layer may be on a top surface of the first gate insulating layer along the periphery of the first nanowire. The first metal layer may have a first crystal grain size. The second metal layer may be on a top surface of the second gate insulating layer along the periphery of the second nanowire. The second metal layer may have a second crystal grain size different from the first crystal grain size.

公开(公告)号：US20180130905A1

公开(公告)日：2018-05-10

申请号：US15620631

申请日：2017-06-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Won Keun CHUNG ,  Jong Ho PARK ,  Seung Ha OH ,  Sang Yong KIM ,  Hoon Joo NA ,  Sang Jin HYUN

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/51 ,  H01L29/06 ,  H01L29/423 ,  H01L21/324 ,  H01L21/283

CPC classification number: H01L29/7831 ,  B82Y10/00 ,  H01L21/283 ,  H01L21/324 ,  H01L29/0653 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/42356 ,  H01L29/42364 ,  H01L29/42392 ,  H01L29/4908 ,  H01L29/511 ,  H01L29/513 ,  H01L29/66439 ,  H01L29/66484 ,  H01L29/66666 ,  H01L29/775 ,  H01L29/7827 ,  H01L29/78696

Abstract: A semiconductor device and a method for fabricating the same are provided. The semiconductor device includes first and second gate stack structures formed in first and second regions, respectively, wherein the first gate stack structure is formed adjacent a first channel region and comprises a first gate insulating film having a first thickness formed on the first channel region, a first function film having a second thickness formed on the first gate insulating film and a first filling film having a third thickness formed on the first function film, wherein the second gate stack structure is formed adjacent a second channel region and comprises a second gate insulating film having the first thickness formed on the second channel region, a second function film having the second thickness formed on the second gate insulating film and a second filling film having the third thickness formed on the second function film, wherein the first and second function films, respectively, comprise TiN and Si concentrations that are different from each other.

公开(公告)号：US20170256544A1

公开(公告)日：2017-09-07

申请号：US15351673

申请日：2016-11-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Young Suk CHAI ,  Hu Yong LEE ,  Sang Yong KIM ,  Taek Soo JEON ,  Won Keun CHUNG ,  Sang Jin HYUN

IPC: H01L27/092 ,  H01L29/423 ,  H01L21/306 ,  H01L21/311 ,  H01L29/51 ,  H01L21/8234

CPC classification number: H01L27/0922 ,  B82Y10/00 ,  H01L21/30604 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/823412 ,  H01L21/823437 ,  H01L21/823462 ,  H01L21/823857 ,  H01L27/088 ,  H01L27/092 ,  H01L29/0673 ,  H01L29/401 ,  H01L29/42364 ,  H01L29/42392 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/78696

Abstract: A semiconductor device including a MOS transistor is provided. The semiconductor device may include a first MOS transistor including first source/drain regions, a first semiconductor layer between the first source/drain regions, a first gate electrode structure, and a first gate dielectric structure; and a second MOS transistor including second source/drain regions, a second semiconductor layer between the second source/drain regions, a second gate electrode structure, and a second gate dielectric structure. The first gate dielectric structure and the second gate dielectric structure include a first common dielectric structure; the first gate dielectric structure includes a first upper dielectric on the first common dielectric structure; the second gate dielectric structure includes the first upper dielectric and a second upper dielectric; and one of the first upper dielectric and the second upper dielectric is a material forming a dipole layer.