公开(公告)号：US20180090493A1

公开(公告)日：2018-03-29

申请号：US15643062

申请日：2017-07-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dae Young Kwak ,  Ki Byung Park ,  Kyoung Hwan Yeo ,  Seung Jae Lee ,  Kyung Yub Jeon ,  Seung Seok Ha ,  Sang Jin Hyun

IPC: H01L27/088 ,  H01L21/8234 ,  H01L29/66

Abstract: Semiconductor devices are provided. A semiconductor device includes a semiconductor substrate. The semiconductor device includes first and second source/drain regions in the semiconductor substrate. Moreover, the semiconductor device includes a multi-layer device isolation region in the semiconductor substrate between the first and second source/drain regions. The multi-layer device isolation region includes a protruding portion that protrudes away from the semiconductor substrate beyond respective uppermost surfaces of the first and second source/drain regions.

公开(公告)号：US10566326B2

公开(公告)日：2020-02-18

申请号：US15643062

申请日：2017-07-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dae Young Kwak ,  Ki Byung Park ,  Kyoung Hwan Yeo ,  Seung Jae Lee ,  Kyung Yub Jeon ,  Seung Seok Ha ,  Sang Jin Hyun

IPC: H01L27/088 ,  H01L21/8234 ,  H01L29/66

Abstract: Semiconductor devices are provided. A semiconductor device includes a semiconductor substrate. The semiconductor device includes first and second source/drain regions in the semiconductor substrate. Moreover, the semiconductor device includes a multi-layer device isolation region in the semiconductor substrate between the first and second source/drain regions. The multi-layer device isolation region includes a protruding portion that protrudes away from the semiconductor substrate beyond respective uppermost surfaces of the first and second source/drain regions.

公开(公告)号：US20190333825A1

公开(公告)日：2019-10-31

申请号：US16507529

申请日：2019-07-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyung Yub Jeon ,  Soo Yeon Jeong ,  Jae Kwang Choi

IPC: H01L21/8234 ,  H01L29/66

Abstract: A method for manufacturing a semiconductor device is provided. A first vertical structure and a second vertical structure are formed on a substrate. The second vertical structure is positioned right next to the first vertical structure. The second vertical structure is positioned right next to the first vertical structure. An insulating layer is formed on the substrate between the first and second vertical structures. A gate metal and a gate dielectric layer, are formed on the first and second vertical structures. A portion of the gate metal, gate dielectric layer, and insulating layer is removed. A portion of the substrate is removed. The portion of the substrate is removed after the gate metal is formed on the first and second vertical structure.

公开(公告)号：US10373878B2

公开(公告)日：2019-08-06

申请号：US15854311

申请日：2017-12-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyung Yub Jeon ,  Soo Yeon Jeong ,  Jae Kwang Choi

IPC: H01L21/8234 ,  H01L29/66

Abstract: A method for manufacturing a semiconductor device is provided. A first vertical structure and a second vertical structure are formed on a substrate. The second vertical structure is positioned right next to the first vertical structure. The second vertical structure is positioned right next to the first vertical structure. An insulating layer is formed on the substrate between the first and second vertical structures. A gate metal and a gate dielectric layer are formed on the first and second vertical structures. A portion of the gate metal, gate dielectric layer, and insulating layer is removed. A portion of the substrate is removed. The portion of the substrate is removed after the gate metal is formed on the first and second vertical structure.

公开(公告)号：US11443988B2

公开(公告)日：2022-09-13

申请号：US17039854

申请日：2020-09-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyung Yub Jeon

IPC: H01L21/8238 ,  H01L21/308 ,  H01L21/311 ,  H01L29/66 ,  H01L29/78 ,  H01L27/092

Abstract: A method for manufacturing a semiconductor is provided. A first oxide layer is formed on a substrate. A first nitride layer is formed on the first oxide layer. A second oxide layer, a second nitride layer are formed on the first nitride layer. A polysilicon layer is formed on the second nitride layer. A third nitride layer is formed on the polysilicon layer. One or more first patterns are formed on the third nitride layer. The one or more first patterns are transferred to the polysilicon layer to form one or more patterned polysilicon layer. A portion of the first oxide layer, first nitride layer, second oxide layer, and second nitride layer are removed using the one or more patterned polysilicon layer as a first mask.

公开(公告)号：US10164057B1

公开(公告)日：2018-12-25

申请号：US15878711

申请日：2018-01-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyung Yub Jeon ,  Tae Yong Kwon ,  Oh Seong Kwon ,  Soo Yeon Jeong ,  Yong Hee Park ,  Jong Ryeol Yoo

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/10 ,  H01L29/423

Abstract: A vertical tunnel field effect transistor (VTFET) including a fin structure protruding from a substrate including a source/drain region, an epitaxially-grown source/drain structure on the fin structure, a cap including pillar portions, the pillar portions covering side surfaces of the epitaxially-grown source/drain structure and partially covering side surfaces of a top portion of the fin structure, a gate insulator covering remaining portions of the side surfaces of the fin structure under the pillar portions of the cap, a work function metal gate on the gate insulator, and a separation pattern surrounding a bottom portion of a fin structure such that the work function metal gate is vertically between the cap and the separation pattern, the separation pattern electrically isolating the work function metal gate from the source/drain region, and a method of manufacturing the same may be provided.

公开(公告)号：US09899497B2

公开(公告)日：2018-02-20

申请号：US15355781

申请日：2016-11-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jin Bum Kim ,  Kang Hun Moon ,  Choeun Lee ,  Kyung Yub Jeon ,  Sujin Jung ,  Haegeon Jung ,  Yang Xu

IPC: H01L29/66 ,  H01L29/08 ,  H01L21/306 ,  H01L21/02

CPC classification number: H01L29/66795 ,  H01L21/02381 ,  H01L21/0243 ,  H01L21/02433 ,  H01L21/02532 ,  H01L21/30604 ,  H01L29/0847 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/7848

Abstract: A method of fabricating a semiconductor device is disclosed. The method includes forming an active pattern protruding orthogonally from a substrate; forming a preliminary gate structure on the active pattern to cross the active pattern; etching the active pattern to form preliminary recess regions at both sides of the preliminary gate structure, wherein each of the preliminary recess regions is formed to define a delta region in an upper portion of the active pattern; forming a sacrificial layer on inner side surfaces and a bottom surface of the active pattern exposed by each of the preliminary recess regions; etching the delta regions and the sacrificial layer to form recess regions having a ‘U’-shaped section; and forming source/drain regions in the recess regions.

公开(公告)号：US10892347B2

公开(公告)日：2021-01-12

申请号：US16197752

申请日：2018-11-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyung Yub Jeon ,  Tae Yong Kwon ,  Oh Seong Kwon ,  Soo Yeon Jeong ,  Yong Hee Park ,  Jong Ryeol Yoo

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/10 ,  H01L29/423 ,  H01L29/786 ,  H01L29/739

Abstract: A vertical tunnel field effect transistor (VTFET) including a fin structure protruding from a substrate including a source/drain region, an epitaxially-grown source/drain structure on the fin structure, a cap including pillar portions, the pillar portions covering side surfaces of the epitaxially-grown source/drain structure and partially covering side surfaces of a top portion of the fin structure, a gate insulator covering remaining portions of the side surfaces of the fin structure under the pillar portions of the cap, a work function metal gate on the gate insulator, and a separation pattern surrounding a bottom portion of a fin structure such that the work function metal gate is vertically between the cap and the separation pattern, the separation pattern electrically isolating the work function metal gate from the source/drain region, and a method of manufacturing the same may be provided.

公开(公告)号：US10804160B2

公开(公告)日：2020-10-13

申请号：US16507529

申请日：2019-07-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyung Yub Jeon ,  Soo Yeon Jeong ,  Jae Kwang Choi

IPC: H01L29/66 ,  H01L21/8234

Abstract: A method for manufacturing a semiconductor device is provided. A first vertical structure and a second vertical structure are formed on a substrate. The second vertical structure is positioned right next to the first vertical structure. The second vertical structure is positioned right next to the first vertical structure. An insulating layer is formed on the substrate between the first and second vertical structures. A gate metal and a gate dielectric layer, are formed on the first and second vertical structures. A portion of the gate metal, gate dielectric layer, and insulating layer is removed. A portion of the substrate is removed. The portion of the substrate is removed after the gate metal is formed on the first and second vertical structure.

公开(公告)号：US10566207B2

公开(公告)日：2020-02-18

申请号：US16135669

申请日：2018-09-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Gyeongseop Kim ,  Kyung Yub Jeon ,  Seul Gi Han

IPC: H01L21/331 ,  H01L21/308 ,  H01L21/311 ,  H01L21/033

Abstract: A method for defining a length of a fin including forming a plurality of first slice walls on a mask material layer, which is provided over the fin, using a plurality of hard mask patterns, providing a plurality of fill mask patterns self-aligned with respect to the plurality of first slice walls to expose one or more select areas between one or more pairs of adjacent ones of the plurality of first slice walls, and providing a trim mask pattern including one or more openings and self-aligned with respect to the plurality of second slice walls to expose one or more of the plurality of first slice walls may be provided.