公开(公告)号：US20140094101A1

公开(公告)日：2014-04-03

申请号：US14117936

申请日：2012-05-15

Applicant: SAMSUNG ELECTRONICS CO., LTD. ,  EHWA DIAMOND INDUSTRIAL CO., LTD.

Inventor： Seh Kwang Lee ,  Youn Chul Kim ,  Joo Han Lee ,  Jae Kwang Choi ,  Jae Phil Boo

IPC: B24B53/017 ,  B24D18/00

CPC classification number: B24B53/017 ,  B24D18/00

Abstract: This invention relates to a conditioner for a CMP (Chemical Mechanical Polishing) pad, which is used in a CMP process which is part of the fabrication of a semiconductor device, and more particularly, to a CMP pad conditioner in which the structure of the cutting tips is such that the change in the wear of the polishing pad is not great even when different kinds of slurry are used and when there are changes in pressure of the conditioner, and to a method of manufacturing the same.

Abstract translation: 本发明涉及一种用于CMP（化学机械抛光）焊盘的调节器，其用于作为半导体器件的制造的一部分的CMP工艺中，更具体地，涉及一种CMP焊盘调节器，其中切割结构 即使使用不同种类的浆料和调节剂的压力变化时，抛光垫的磨损变化也不是很大，而且制造方法也是如此。

公开(公告)号：US20180315662A1

公开(公告)日：2018-11-01

申请号：US15854311

申请日：2017-12-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： KYUNG YUB JEON ,  Soo Yeon Jeong ,  Jae Kwang Choi

IPC: H01L21/8234

CPC classification number: H01L21/823487 ,  H01L21/823418 ,  H01L21/823437 ,  H01L21/823481 ,  H01L29/66666

Abstract: A method for manufacturing a semiconductor device is provided. A first vertical structure and a second vertical structure are formed on a substrate. The second vertical structure is positioned right next to the first vertical structure. The second vertical structure is positioned right next to the first vertical structure. An insulating layer is formed on the substrate between the first and second vertical structures. A gate metal and a gate dielectric layer are formed on the first and second vertical structures. A portion of the gate metal, gate dielectric layer, and insulating layer is removed. A portion of the substrate is removed. The portion of the substrate is removed after the gate metal is formed on the first and second vertical structure.

公开(公告)号：US20190333825A1

公开(公告)日：2019-10-31

申请号：US16507529

申请日：2019-07-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyung Yub Jeon ,  Soo Yeon Jeong ,  Jae Kwang Choi

IPC: H01L21/8234 ,  H01L29/66

Abstract: A method for manufacturing a semiconductor device is provided. A first vertical structure and a second vertical structure are formed on a substrate. The second vertical structure is positioned right next to the first vertical structure. The second vertical structure is positioned right next to the first vertical structure. An insulating layer is formed on the substrate between the first and second vertical structures. A gate metal and a gate dielectric layer, are formed on the first and second vertical structures. A portion of the gate metal, gate dielectric layer, and insulating layer is removed. A portion of the substrate is removed. The portion of the substrate is removed after the gate metal is formed on the first and second vertical structure.

公开(公告)号：US10373878B2

公开(公告)日：2019-08-06

申请号：US15854311

申请日：2017-12-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyung Yub Jeon ,  Soo Yeon Jeong ,  Jae Kwang Choi

IPC: H01L21/8234 ,  H01L29/66

Abstract: A method for manufacturing a semiconductor device is provided. A first vertical structure and a second vertical structure are formed on a substrate. The second vertical structure is positioned right next to the first vertical structure. The second vertical structure is positioned right next to the first vertical structure. An insulating layer is formed on the substrate between the first and second vertical structures. A gate metal and a gate dielectric layer are formed on the first and second vertical structures. A portion of the gate metal, gate dielectric layer, and insulating layer is removed. A portion of the substrate is removed. The portion of the substrate is removed after the gate metal is formed on the first and second vertical structure.

公开(公告)号：US10804160B2

公开(公告)日：2020-10-13

申请号：US16507529

申请日：2019-07-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyung Yub Jeon ,  Soo Yeon Jeong ,  Jae Kwang Choi

IPC: H01L29/66 ,  H01L21/8234

Abstract: A method for manufacturing a semiconductor device is provided. A first vertical structure and a second vertical structure are formed on a substrate. The second vertical structure is positioned right next to the first vertical structure. The second vertical structure is positioned right next to the first vertical structure. An insulating layer is formed on the substrate between the first and second vertical structures. A gate metal and a gate dielectric layer, are formed on the first and second vertical structures. A portion of the gate metal, gate dielectric layer, and insulating layer is removed. A portion of the substrate is removed. The portion of the substrate is removed after the gate metal is formed on the first and second vertical structure.